Abstract: An arithmetic logic circuit comprising a plurality of cells of conventional logic circuits for performing logical and arithmetic operations in combination with a kill circuit in each one of the cells which is responsive to bits of first and second operands T and B, a clock signal .0.1*, a propagate bit P and a carry-in bit C.sub.in for selectively providing a carry-out bit C.sub.out and/or a carry-bypass circuit coupled to each one of a plurality of sets of cells which is responsive to propagate bits P from said cells in each set, a clock signal .0.2* and a carry-in bit C.sub.in for allowing said carry-in bit C.sub.in to bypass selected ones of the cells.