Patents by Inventor Flynn Carson

Flynn Carson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7750454
    Abstract: A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated circuit package.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: July 6, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: Flynn Carson, Jong-Woo Ha, BumJoon Hong, SeongMin Lee
  • Patent number: 7741154
    Abstract: An integrated circuit package system comprising: providing a module lead array; attaching a module integrated circuit adjacent the module lead array; attaching a module substrate over the module integrated circuit; and applying a module encapsulant over the module integrated circuit wherein the module lead array and the module substrate are partially exposed.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 22, 2010
    Assignee: STATS Chippac Ltd.
    Inventors: Jong-Woo Ha, Flynn Carson, BumJoon Hong, SeongMin Lee
  • Publication number: 20100148344
    Abstract: An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 17, 2010
    Inventors: Harry Chandra, Flynn Carson
  • Publication number: 20100136744
    Abstract: A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.
    Type: Application
    Filed: February 3, 2010
    Publication date: June 3, 2010
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Patent number: 7692279
    Abstract: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: April 6, 2010
    Assignee: Chippac, Inc.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Patent number: 7687315
    Abstract: An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: March 30, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventor: Flynn Carson
  • Publication number: 20100072582
    Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 25, 2010
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Harry Chandra, Flynn Carson
  • Publication number: 20090243072
    Abstract: A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer exposed by the cavity, over the base integrated circuit package.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Inventors: Jong-Woo Ha, Flynn Carson, BumJoon Hong, SeongMin Lee
  • Publication number: 20090243073
    Abstract: A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated circuit package.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Inventors: Flynn Carson, Jong-Woo Ha, BumJoon Hong, SeongMin Lee
  • Publication number: 20090243071
    Abstract: An integrated circuit package system comprising: providing a module lead array; attaching a module integrated circuit adjacent the module lead array; attaching a module substrate over the module integrated circuit; and applying a module encapsulant over the module integrated circuit wherein the module lead array and the module substrate are partially exposed.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 1, 2009
    Inventors: Jong-Woo Ha, Flynn Carson, BumJoon Hong, SeongMin Lee
  • Publication number: 20090108428
    Abstract: A mountable integrated circuit package system includes: providing a carrier; mounting a first integrated circuit device over the carrier; mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess; connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the first integrated circuit device; and forming a package encapsulation over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 30, 2009
    Inventors: Flynn Carson, In Sang Yoon, SeongMin Lee, JoHyun Bae
  • Patent number: 7494847
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a wire bond carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper wire bond carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: February 24, 2009
    Assignee: ChipPac, Inc.
    Inventors: Marcos Karnezos, Flynn Carson
  • Publication number: 20080258289
    Abstract: An integrated circuit package system comprising: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 23, 2008
    Inventors: Rajendra D. Pendse, Flynn Carson, Il Kwon Shim, Seng Guan Chow
  • Patent number: 7429786
    Abstract: A semiconductor package subassembly includes a die affixed to, and electrically interconnected with, a die attach side of a first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the first package with the first side of the second substrate facing the die attach side of the first package substrate, and supported by a spacer or a spacer assembly. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 30, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Marcos Karnezos, Flynn Carson
  • Publication number: 20080169549
    Abstract: An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.
    Type: Application
    Filed: March 10, 2008
    Publication date: July 17, 2008
    Inventor: Flynn Carson
  • Patent number: 7354800
    Abstract: An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: April 8, 2008
    Assignee: Stats Chippac Ltd.
    Inventor: Flynn Carson
  • Publication number: 20080020512
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a wire bond carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper wire bond carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Application
    Filed: July 23, 2007
    Publication date: January 24, 2008
    Inventors: Marcos Karnezos, Flynn Carson
  • Publication number: 20070278658
    Abstract: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die.
    Type: Application
    Filed: July 2, 2007
    Publication date: December 6, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Patent number: 7253511
    Abstract: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: August 7, 2007
    Assignee: ChipPAC, Inc.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Publication number: 20070176289
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Application
    Filed: April 6, 2007
    Publication date: August 2, 2007
    Applicant: ChipPAC, Inc
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos