Patents by Inventor Fong Lim
Fong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262732Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.Type: GrantFiled: April 24, 2018Date of Patent: April 16, 2019Assignee: Winbond Electronics Corp.Inventors: Seow Fong Lim, Chi-Shun Lin, Douk-Hyoun Ryu, Ngatik Cheung
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Patent number: 10261692Abstract: An erase controlling method includes: disposing a plurality of sectors in a memory block of the non-volatile memory; disposing a plurality of auxiliary sectors that respectively correspond to the sectors, wherein each of the sectors shares same word lines with the corresponding auxiliary sector; respectively storing a plurality of erase counting values of the sectors to the auxiliary sectors; generating a total amount of the erase counting values; and, determining whether to perform a refresh operation on the memory block according to the total amount.Type: GrantFiled: December 20, 2017Date of Patent: April 16, 2019Assignee: Winbond Electronics Corp.Inventor: Seow Fong Lim
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Publication number: 20190088321Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.Type: ApplicationFiled: August 31, 2018Publication date: March 21, 2019Applicant: Winbond Electronics Corp.Inventors: Lih-Wei Lin, Tsung-Huan Tsai, Chi-Shun Lin, Seow Fong Lim
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Publication number: 20190065307Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Ming-Huei Shieh, Seow-Fong Lim, Ngatik Cheung, Chi-Shun Lin
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Patent number: 10216570Abstract: A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.Type: GrantFiled: January 31, 2017Date of Patent: February 26, 2019Assignee: Winbond Electronics CorporationInventors: Hsi-Hsien Hung, Seow Fong Lim
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Patent number: 10210917Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.Type: GrantFiled: January 11, 2018Date of Patent: February 19, 2019Assignee: Unity Semiconductor CorporationInventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
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Publication number: 20190043575Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.Type: ApplicationFiled: April 24, 2018Publication date: February 7, 2019Applicant: Winbond Electronics Corp.Inventors: Seow Fong Lim, Chi-Shun Lin, Douk-Hyoun Ryu, Ngatik Cheung
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Publication number: 20180342268Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: ApplicationFiled: May 18, 2018Publication date: November 29, 2018Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Publication number: 20180309453Abstract: A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.Type: ApplicationFiled: April 21, 2017Publication date: October 25, 2018Inventors: Seow Fong LIM, Chi-Shun LIN
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Patent number: 10100708Abstract: Disclosed is an engine temperature regulating device installed to a cool air inlet of a casing of an engine. The engine temperature regulating device includes a power source, a link rod module connected to the power source, a control module and a fan cover module including a fixed casing and a movable casing. The control module is provided for detecting a temperature when the engine is turned on to control the power source to drive the link rod module, so as to control the rotation of the connected movable casing and further adjust an air intake hole of the fixed casing to a smooth or obscured state.Type: GrantFiled: November 28, 2016Date of Patent: October 16, 2018Assignee: Southern Taiwan University of Science and TechnologyInventors: Cho Yu Lee, Jui Hung Chang, Chin Fong Lim
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Publication number: 20180226110Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.Type: ApplicationFiled: January 11, 2018Publication date: August 9, 2018Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
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Publication number: 20180217893Abstract: A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.Type: ApplicationFiled: January 31, 2017Publication date: August 2, 2018Inventors: Hsi-Hsien HUNG, Seow Fong LIM
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Patent number: 10032512Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.Type: GrantFiled: July 5, 2017Date of Patent: July 24, 2018Assignee: Winbond Electronics Corp.Inventors: Makoto Senoo, Seow-Fong Lim
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Patent number: 10002646Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: GrantFiled: October 29, 2014Date of Patent: June 19, 2018Assignee: Unity Semiconductor CorporationInventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Publication number: 20180149072Abstract: Disclosed is an engine temperature regulating device installed to a cool air inlet of a casing of an engine. The engine temperature regulating device includes a power source, a link rod module connected to the power source, a control module and a fan cover module including a fixed casing and a movable casing. The control module is provided for detecting a temperature when the engine is turned on to control the power source to drive the link rod module, so as to control the rotation of the connected movable casing and further adjust an air intake hole of the fixed casing to a smooth or obscured state.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: CHO YU LEE, JUI HUNG CHANG, CHIN FONG LIM
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Patent number: 9870809Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.Type: GrantFiled: June 29, 2016Date of Patent: January 16, 2018Assignee: Unity Semiconductor CorporationInventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
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Publication number: 20180012655Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.Type: ApplicationFiled: July 5, 2017Publication date: January 11, 2018Applicant: Winbond Electronics Corp.Inventors: Makoto Senoo, Seow-Fong Lim
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Patent number: 9859000Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.Type: GrantFiled: June 17, 2016Date of Patent: January 2, 2018Assignee: Winbond Electronics Corp.Inventors: Chi-Shun Lin, Ngatik Cheung, Douk-Hyoun Ryu, Seow-Fong Lim, Koying Huang
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Publication number: 20170373559Abstract: A low impedance power disc is provided. The power disc is connected to a crankshaft of an engine, and includes a rotor, a connecting shaft, and a permanent magnet. The rotor is disposed separately from the permanent magnet. The connecting shaft is locked inside the rotor. A unidirectional bearing is provided and fitted on the connecting shaft. The permanent magnet is fitted on the unidirectional bearing. When the engine is running, the rotor and the permanent magnet are rotated at the same speed to generate electricity and supply the electricity to the vehicle and to charge the battery. When the engine decelerates, the rotor and the connecting shaft are decelerated synchronously with the engine, while the permanent magnet and the unidirectional bearing are continuously rotated at the speed before deceleration in order to facilitate the engine to accelerate again, so that the rotor can be quickly rotated.Type: ApplicationFiled: June 14, 2017Publication date: December 28, 2017Inventors: CHO YU LEE, JUI HUNG CHANG, CHIN FONG LIM
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Publication number: 20170365336Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.Type: ApplicationFiled: June 17, 2016Publication date: December 21, 2017Inventors: Chi-Shun Lin, Ngatik Cheung, Douk-Hyoun Ryu, Seow-Fong Lim, Koying Huang