Patents by Inventor Fong Lim

Fong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180309453
    Abstract: A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Inventors: Seow Fong LIM, Chi-Shun LIN
  • Patent number: 10100708
    Abstract: Disclosed is an engine temperature regulating device installed to a cool air inlet of a casing of an engine. The engine temperature regulating device includes a power source, a link rod module connected to the power source, a control module and a fan cover module including a fixed casing and a movable casing. The control module is provided for detecting a temperature when the engine is turned on to control the power source to drive the link rod module, so as to control the rotation of the connected movable casing and further adjust an air intake hole of the fixed casing to a smooth or obscured state.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 16, 2018
    Assignee: Southern Taiwan University of Science and Technology
    Inventors: Cho Yu Lee, Jui Hung Chang, Chin Fong Lim
  • Publication number: 20180226110
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Application
    Filed: January 11, 2018
    Publication date: August 9, 2018
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Publication number: 20180217893
    Abstract: A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.
    Type: Application
    Filed: January 31, 2017
    Publication date: August 2, 2018
    Inventors: Hsi-Hsien HUNG, Seow Fong LIM
  • Patent number: 10032512
    Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: July 24, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Makoto Senoo, Seow-Fong Lim
  • Patent number: 10002646
    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 19, 2018
    Assignee: Unity Semiconductor Corporation
    Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
  • Publication number: 20180149072
    Abstract: Disclosed is an engine temperature regulating device installed to a cool air inlet of a casing of an engine. The engine temperature regulating device includes a power source, a link rod module connected to the power source, a control module and a fan cover module including a fixed casing and a movable casing. The control module is provided for detecting a temperature when the engine is turned on to control the power source to drive the link rod module, so as to control the rotation of the connected movable casing and further adjust an air intake hole of the fixed casing to a smooth or obscured state.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: CHO YU LEE, JUI HUNG CHANG, CHIN FONG LIM
  • Patent number: 9870809
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 16, 2018
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Publication number: 20180012655
    Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 11, 2018
    Applicant: Winbond Electronics Corp.
    Inventors: Makoto Senoo, Seow-Fong Lim
  • Patent number: 9859000
    Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 2, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Chi-Shun Lin, Ngatik Cheung, Douk-Hyoun Ryu, Seow-Fong Lim, Koying Huang
  • Publication number: 20170373559
    Abstract: A low impedance power disc is provided. The power disc is connected to a crankshaft of an engine, and includes a rotor, a connecting shaft, and a permanent magnet. The rotor is disposed separately from the permanent magnet. The connecting shaft is locked inside the rotor. A unidirectional bearing is provided and fitted on the connecting shaft. The permanent magnet is fitted on the unidirectional bearing. When the engine is running, the rotor and the permanent magnet are rotated at the same speed to generate electricity and supply the electricity to the vehicle and to charge the battery. When the engine decelerates, the rotor and the connecting shaft are decelerated synchronously with the engine, while the permanent magnet and the unidirectional bearing are continuously rotated at the speed before deceleration in order to facilitate the engine to accelerate again, so that the rotor can be quickly rotated.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 28, 2017
    Inventors: CHO YU LEE, JUI HUNG CHANG, CHIN FONG LIM
  • Publication number: 20170365336
    Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.
    Type: Application
    Filed: June 17, 2016
    Publication date: December 21, 2017
    Inventors: Chi-Shun Lin, Ngatik Cheung, Douk-Hyoun Ryu, Seow-Fong Lim, Koying Huang
  • Patent number: 9576652
    Abstract: The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line selecting switch, a first pull down switch and a second pull down switch. The first bit line selecting switch is coupled between a first bit line and a sense amplifier. The first source line selecting switch is coupled between a source line and the sense amplifier. The first and second pull down switches are respectively coupled to the bit line and source line. When a reading operation is operated, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: February 21, 2017
    Assignee: Winbond Electronics Corp.
    Inventors: Seow-Fong Lim, Johnny Chan, Douk-Hyoun Ryu, Chi-Shun Lin
  • Publication number: 20160379692
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Application
    Filed: June 29, 2016
    Publication date: December 29, 2016
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Patent number: 9384806
    Abstract: A memory device includes a plurality of memory layers and a selecting circuit configured to select a delta value corresponding to a parameter of at least one of the plurality of memory layers having fabricated thereon at least one memory cell accessed during an operation. The memory device further includes an adjusting circuit configured to adjust an access signal based at least in part on the delta value, the access signal being configured to access the at least one memory cell during the operation.
    Type: Grant
    Filed: August 15, 2015
    Date of Patent: July 5, 2016
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Publication number: 20150364169
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Application
    Filed: August 15, 2015
    Publication date: December 17, 2015
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Patent number: 9129668
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: September 8, 2015
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Publication number: 20150132917
    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 14, 2015
    Inventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
  • Patent number: 8975117
    Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Fong Lim, Abdul Rahman Mohamed, Chooi Mei Chong, Ida Fischbach, Xaver Schloegel, Juergen Schredl, Josef Hoeglauer
  • Publication number: 20150055425
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Application
    Filed: September 3, 2014
    Publication date: February 26, 2015
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau