Abstract: A device includes gate-all-around transistors and method for manufacturing such a device. A method for manufacturing a microelectronic device includes at least two transistors each comprising a channel in the shape of a wire extending in a first direction x, a gate surrounding said channel, a source and a drain, said transistors being stacked in a third direction z and each occupying a level nz (z=1 . . . 4) of given altitude in the third direction z.

Abstract: An image sensor including a plurality of pixels, each pixel including a photodetector coupled to a control circuit, the photodetector being formed inside and on top of a first semiconductor substrate, and the control circuit including at least one first MOS transistor formed inside and on top of a second semiconductor substrate arranged on the first substrate, the sensor being intended to be illuminated on the side of the surface of the first substrate opposite to the second substrate, the sensor further comprising a shield arranged between the first and second substrates and extending over substantially the entire surface of the sensor, said shield including at least one electrically-conductive layer.

Abstract: An FDSOI transistor control device includes a plurality of first wells having a first type of conductivity, each first well being associated with a group of transistors, and at least one second well having a second type of conductivity, formed under and around the first wells (21). A bias circuit is configured to apply at least one first bias voltage to the first wells and at least one second bias voltage to at least one second well. All of the transistors may have the second type of conductivity.

Abstract: A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.

Abstract: A memory device is provided with a support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between a first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resist memory cells are arranged.

Abstract: A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.

Abstract: The present invention relates to a neuromorphic circuit suitable for implementing a neural network, the neuromorphic circuit comprising: lines of words, pairs of complementary bit-lines, source lines, a set of elementary cells, an electronic circuit implementing a neurone having an output and including: a set of logic components, a counting unit, a comparison unit comprising a comparator and a comparison voltage generator, the comparator being suitable for comparing the output of the counting unit with the comparison voltage generated by the comparison voltage generator in order to output a signal dependent on the comparison and corresponding to the output of the electronic circuit which implements a neurone.

Abstract: A memory structured in lines and columns over several superimposed levels, each level comprising an array of memory elements and gate-all-around access transistors, each transistor including a semiconductor nanowire and each gate being insulated from the gates of the other levels, further comprising: conductive portions, each crossing at least two levels and coupled to first ends of the nanowires of one column of the levels; memory stacks, each crossing the levels and coupled to second ends of the nanowires of said column; first conductive lines, each connected to the conductive portions of the same column; word lines each extending in the same level while coupling together the gates of the same line and located in said level.

Abstract: The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.

Abstract: The invention relates to a method of forming a trapping structure of a useful substrate designed to trap charges and limit at least one of crosstalk, radio frequency losses, and distortions of a device that may be formed on or in the useful substrate. Formation of the trapping structure includes forming a first layer that includes amorphous silicon carbide and forming a second layer covering the first layer that comprises an insulating or semiconductor material in an amorphous state and having a crystallisation temperature lower than that of the amorphous silicon carbide.

Abstract: The invention relates to a method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, said device comprising active components (23) formed in active areas of the substrate (10) separated by isolation trenches and which are delimited by first sidewalls (19B), said isolation trenches being filled, at least partially, with a first dielectric material, the method comprising: a step of chemically attacking a passive section (21) of the first bottom of the isolation trenches intended to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm, a step of forming a passive component (27), covering the first dielectric material and directly above the passive section (21).

Abstract: A production of a device with superimposed levels of components including in this order providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2, above said given level N1, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.

Abstract: A device includes gate-all-around transistors and method for manufacturing such a device. A method for manufacturing a microelectronic device includes at least two transistors each comprising a channel in the shape of a wire extending in a first direction x, a gate surrounding said channel, a source and a drain, said transistors being stacked in a third direction z and each occupying a level nz (z=1 . . . 4) of given altitude in the third direction z.

Abstract: The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.

Abstract: Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.

Abstract: A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.

Abstract: An image sensor including a plurality of pixels, each pixel including a photodetector coupled to a control circuit, the photodetector being formed inside and on top of a first semiconductor substrate, and the control circuit including at least one first MOS transistor formed inside and on top of a second semiconductor substrate arranged on the first substrate, the sensor being intended to be illuminated on the side of the surface of the first substrate opposite to the second substrate, the sensor further comprising a shield arranged between the first and second substrates and extending over substantially the entire surface of the sensor, said shield including at least one electrically-conductive layer.

Abstract: A memory device is provided support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resistive memory cells are arranged.

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.