Patents by Inventor François Andrieu

François Andrieu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11139209
    Abstract: A production of a device with superimposed levels of components including in this order providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2, above said given level N1, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 5, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Francois Andrieu
  • Publication number: 20210296398
    Abstract: A device includes gate-all-around transistors and method for manufacturing such a device. A method for manufacturing a microelectronic device includes at least two transistors each comprising a channel in the shape of a wire extending in a first direction x, a gate surrounding said channel, a source and a drain, said transistors being stacked in a third direction z and each occupying a level nz (z=1 . . . 4) of given altitude in the third direction z.
    Type: Application
    Filed: December 23, 2020
    Publication date: September 23, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, François ANDRIEU
  • Publication number: 20210193738
    Abstract: The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 24, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, François ANDRIEU
  • Patent number: 11024544
    Abstract: Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 1, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Lamine Benaissa, Laurent Brunet
  • Patent number: 11011425
    Abstract: A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 18, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Francois Andrieu, Maud Vinet
  • Publication number: 20210082983
    Abstract: An image sensor including a plurality of pixels, each pixel including a photodetector coupled to a control circuit, the photodetector being formed inside and on top of a first semiconductor substrate, and the control circuit including at least one first MOS transistor formed inside and on top of a second semiconductor substrate arranged on the first substrate, the sensor being intended to be illuminated on the side of the surface of the first substrate opposite to the second substrate, the sensor further comprising a shield arranged between the first and second substrates and extending over substantially the entire surface of the sensor, said shield including at least one electrically-conductive layer.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 18, 2021
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Lina Kadura, François Andrieu, Perrine Batude, Christophe Licitra
  • Publication number: 20210028231
    Abstract: A memory device is provided support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resistive memory cells are arranged.
    Type: Application
    Filed: March 26, 2019
    Publication date: January 28, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: François ANDRIEU
  • Patent number: 10777680
    Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 15, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Francois Andrieu
  • Patent number: 10741565
    Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 11, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon, Bastien Giraud
  • Publication number: 20200203229
    Abstract: Production of a device with superimposed levels of components including in this order: a) providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2 above said given level N1, said stack including a so-called ground plane layer made of conductor or semiconductor material or doped semiconductor material situated between the first semiconductor layer and the second semiconductor layer as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer, b) forming a gate of a transistor on at least one island among said one or more islands, c) defining by etching distinct portions in the second semiconductor ground plane layer so as to free a space around at least one first etched portion of the ground plane layer arranged under an
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Francois Andrieu
  • Publication number: 20200194273
    Abstract: Method for producing a semiconductor substrate, including the implementation of the following steps: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the strained semiconductor region; etching the superficial layer according to a pattern of the etching mask, exposing at least one first lateral edge formed by a first strained semiconductor portion belonging to said part of the strained semiconductor region and which is in contact with the buried dielectric layer; modifying the first strained semiconductor portion into a second portion of material forming a mechanical support element arranged against the strained semiconductor region; removing the etching mask.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 18, 2020
    Applicant: Commissariat A L 'Energie Atomique et aux Energies Alternatives
    Inventors: Shay REBOH, Victor Boureau, Sylvain Maitrejean, Francois Andrieu
  • Patent number: 10651202
    Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 12, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Perrine Batude, Maud Vinet
  • Publication number: 20200035561
    Abstract: Production of a 3D microelectronic device including: assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.
    Type: Application
    Filed: July 29, 2019
    Publication date: January 30, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Francois ANDRIEU, Maud VINET
  • Patent number: 10546929
    Abstract: An integrated circuit includes a substrate; a buried insulating layer; at least one nMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one pMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one semiconductor groundplane that may be doped or a metal, placed above the substrate and below the buried insulating layer, said buried plane being common to the nMOS transistor and to the pMOS transistor; at least one gate insulator and a gate that is common to the nMOS transistor and to the pMOS transistor and that is located above the channel of these transistors and facing the groundplane, the area of the groundplane at least covering the area of the gate in vertical projection; the nMOS transistor being separated from the pMOS transistor by an isolation defined between the semiconductor layer of the nMOS transistor and the semiconductor layer of the pMOS transistor, the isolation being located in the buried insulating l
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 28, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: François Andrieu, Remy Berthelon
  • Patent number: 10504897
    Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 10, 2019
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon
  • Publication number: 20190363190
    Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.
    Type: Application
    Filed: August 7, 2019
    Publication date: November 28, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy BERTHELON, Francois ANDRIEU
  • Patent number: 10446548
    Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: October 15, 2019
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon
  • Publication number: 20190312039
    Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon, Bastien Giraud
  • Patent number: 10418486
    Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 17, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Francois Andrieu
  • Publication number: 20190198397
    Abstract: Fabrication of a circuit with superposed transistors, comprising assembly of a structure comprising transistors formed from a first semiconducting layer with a support (100) provided with a second semiconducting layer (102) in which transistors are provided on a higher level (N2), the second semiconducting layer (102) being coated with a thin layer (101) of silicon oxide, the assembly of said structure and the support (100) being made by direct bonding in which the thin silicon oxide layer (101) is bonded to oxidised portions (37b, 37c) of getter material.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 27, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois ANDRIEU, Lamine Benaissa, Laurent Brunet