Abstract: An interface apparatus for coupling a vehicle to a container, has: a base engageable by the vehicle; a frame connected to the base and detachably securable to the container, the frame pivotable relative to the base for pivoting the container from a lifting position to a discharging position for discharging the container; an actuation unit between the frame and the base; and a latching mechanism for removably attaching the container to the apparatus, the latching mechanism including a first portion secured to the frame and a second portion securable to the container, the first portion movable relative to the second portion in a mating direction having a component normal to the ground from a disengaged configuration in which the first portion is detached form the second portion to an engaged configuration in which the first portion is received within the second portion.

Abstract: The present invention relates to a flexible sheet of wood strips for use in the fabrication of engineered floor boards or wood sheets and including the machine and method of manufacture of the flexible sheet of wood strips. The wood strips provide a wood floor which has much more stability than a solid wood plank which is much more affected by the temperature in a room and the moisture under the floor board. Also solid wood planks are much more expensive than engineered wood planks where only a very thin layer of quality wood material is utilized. The transverse wood strips are constructed of inferior wood material. Two or more treads of flexible material may be secured transversely to the wood strips to provide additional retention of the wood strips in the flexible sheet.

Abstract: A method for determining an estimated duration before a technical incident in a computing infrastructure, executed by a computing device. The computing device including a data processing module, a storage module that stores in memory at least one correlation base between performance indicators, wherein the correlation base includes values of duration before becoming anomalous between correlated performance indicators, and a collection module. The method includes receiving performance indicator values, identifying anomalous performance indicators, identifying first and other at-risk indicators. The method includes determining an estimated duration before a technical incident including a calculation, from the anomalous indicators and at-risk indicators, a shorter path leading to a risk of technical incident, and a calculation of an estimated duration before a technical incident.

Abstract: This application is directed to a method of managing processing capability of a server system having one or more processing cores that further include multiple processing slices. Upon receiving requests to initiate online gaming sessions, the server system allocates each processing slice of the processing cores to a subset of the online gaming sessions to be executed thereon. A first processing slice is allocated to a first subset of the online gaming sessions including a first gaming session and a second gaming session. At the first processing slice, a time-sharing processing schedule is determined for the first subset of the online gaming sessions. In accordance with the time-sharing processing schedule, the first and second gaming sessions share a duty cycle of the first processing slice, and are executed dynamically and in parallel according to real-time data processing need of the first and second gaming sessions.

Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.

Abstract: A method and system of supplementing a main illuminating light with a supplementary illuminating light using a plurality of solid-state light emitters to illuminate a space according to a target illumination spectrum are provided. The method can include determining or receiving a reference illumination spectrum associated with the main illuminating light. The method can also include determining a spectral deviation between the reference illumination spectrum and the target illumination spectrum. The method can further include controlling the solid-state light emitters to emit respective emitter beams forming the supplementary illuminating light and illuminating the space along with the main illuminating light, the emitter beams having respective emitter spectra together defining a supplementary illumination spectrum of the supplementary illuminating light.

Abstract: Methods and systems are provided for generating a dynamic lighting scenario over a scenario timeline using solid-state light emitters. The method can include a step of providing a plurality of lighting reference points in the dynamic lighting scenario, each lighting reference point having an associated reference illumination state to be achieved at a corresponding reference moment of the scenario timeline. The method can also include a step of determining a plurality of sets of reference control parameters for the solid-state light emitters, each set of reference control parameters for producing the reference illumination state associated to a corresponding one of the plurality of lighting reference points. The method can also include driving the solid-state light emitters based on the plurality of reference control parameters to generate the dynamic lighting scenario.

Abstract: This application is directed to a method of managing processing capability of a server system having one or more processing cores that further include multiple processing slices. Upon receiving requests to initiate online gaming sessions, the server system allocates each processing slice of the processing cores to a subset of the online gaming sessions to be executed thereon. A first processing slice is allocated to a first subset of the online gaming sessions including a first gaming session and a second gaming session. At the first processing slice, a time-sharing processing schedule is determined for the first subset of the online gaming sessions. In accordance with the time-sharing processing schedule, the first and second gaming sessions share a duty cycle of the first processing slice, and are executed dynamically and in parallel according to real-time data processing need of the first and second gaming sessions.

Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.

Abstract: A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

Abstract: Some implementations of this application are directed to a server system including one or more CPUs, a plurality of GPUs, main dynamic memory storing programs and data for use by the CPUs and/or GPUs during program execution, a static memory pool stored in a non-volatile memory, and a memory controller configured to manage the static memory pool. Each of the GPUs includes a local cache and is configured to access the static memory pool via the memory controller. The server system executes a plurality of gaming sessions for a gaming title in parallel on the one or more CPUs. Each of the plurality of gaming sessions is associated with a static data item stored in the static memory pool, and requires a graphics operation executable by a respective GPU using the static data item.

Abstract: A device for stretching a canvas mounted to a frame comprises a spacer and a screw. The frame has a plurality of side members each mutually abutting at angled ends. A first portion of the spacer includes a central aperture therethrough and two opposing ends or sides. Each end of the first portion is sized to engage a contact surface of each side member. The screw has a threaded shaft adapted for rotational engagement with the central aperture of the first portion of the spacer. The threaded shaft terminates at a first end thereof with a screw head that has a frustoconical side wall and an end surface that includes a tool-engaging recess. Rotating the screw to move the screw head closer to the spacer causes the spacer to push the side members mutually away from each other to stretch the canvas.

Abstract: Debugging a graphics application executing on a target device. The graphics application may execute CPU instructions to generate graphics commands to graphics hardware for generation of graphics on a display. A breakpoint for the graphics application may be detected at a first time. In response to detecting the breakpoint, one or more graphics commands which were executed by the graphics hardware proximate to the first time may be displayed. Additionally, source code corresponding to CPU instructions which generated the one or more graphics commands may be displayed.

Abstract: Some implementations of this application are directed to a server system including one or more CPUs, a plurality of GPUs, main dynamic memory storing programs and data for use by the CPUs and/or GPUs during program execution, a static memory pool stored in a non-volatile memory, and a memory controller configured to manage the static memory pool. Each of the GPUs includes a local cache and is configured to access the static memory pool via the memory controller. The server system executes a plurality of gaming sessions for a gaming title in parallel on the one or more CPUs. Each of the plurality of gaming sessions is associated with a static data item stored in the static memory pool, and requires a graphics operation executable by a respective GPU using the static data item.

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

Abstract: An image sensor includes a pixel with a photosensitive region accommodated within a semiconductor substrate and a MOS capacitive element with a conducting electrode electrically isolated by a dielectric layer. The dielectric layer forms an interface with both the photosensitive region and the semiconductor substrate, the interface of the dielectric layer including charge traps. A control circuit biases the electrode of the MOS capacitive element with a charge pumping signal designed to generate an alternation of successive inversion regimes and accumulation regimes in the photosensitive region. The charge pumping signal produces recombinations of photogenerated charges in the charge traps of the interface of the dielectric layer and the generation of a substrate current to empty recombined photogenerated charges.