Abstract: The present disclosure provides a graphene based dry electrode for electrophysiological readings, in particular for use with EEG, EKG, EMG, and EOG systems and a method for making said electrodes. The electrodes comprising a doped silicon substrate; a silicon carbide film on the substrate; a graphene surface on the silicon carbide film; wherein the graphene surface has undergone a functionalisation and/or intercalation process to increase the amount of oxygen functional groups present, said process being preferably carried out through repeated contact of the graphene surface with an electrolyte solution.

Abstract: An electrical isolation process, includes receiving a substrate including a layer of carbon-rich material on silicon, and selectively removing regions of the substrate to form mutually spaced islands of the carbon-rich material on the silicon. The layer of carbon-rich material on silicon includes the layer of carbon-rich material on an electrically conductive layer of silicon on an electrically insulating material. Selectively removing regions of the substrate includes removing the carbon-rich material and at least a portion of the electrically conductive layer of silicon from those regions to provide electrical isolation between the islands of carbon-rich material on silicon.

Abstract: A process for forming high surface area graphene structures includes: depositing at least one metal on a surface of silicon carbide; heating the at least one metal and the silicon carbide to cause at least one of the metals to react with a portion of the silicon carbide to form silicide regions extending into an unreacted portion of the silicon carbide and graphene disposed between the silicide regions and the unreacted portion of the silicon carbide; and removing the silicide regions to provide a silicon carbide structure having a highly irregular surface and a surface layer of graphene.

Abstract: An electrical isolation process, includes receiving a substrate including a layer of carbon-rich material on silicon, and selectively removing regions of the substrate to form mutually spaced islands of the carbon-rich material on the silicon. The layer of carbon-rich material on silicon includes the layer of carbon-rich material on an electrically conductive layer of silicon on an electrically insulating material. Selectively removing regions of the substrate includes removing the carbon-rich material and at least a portion of the electrically conductive layer of silicon from those regions to provide electrical isolation between the islands of carbon-rich material on silicon.

Abstract: A process for forming high surface area graphene structures includes: depositing at least one metal on a surface of silicon carbide; heating the at least one metal and the silicon carbide to cause at least one of the metals to react with a portion of the silicon carbide to form silicide regions extending into an unreacted portion of the silicon carbide and graphene disposed between the silicide regions and the unreacted portion of the silicon carbide; and removing the silicide regions to provide a silicon carbide structure having a highly irregular surface and a surface layer of graphene.

Abstract: A process for forming graphene, includes: depositing at least a first and a second metal onto a surface of silicon carbide (SiC), and heating the SiC and the first and second metals under conditions that cause the first metal to react with silicon of the silicon carbide to form carbon and at least one stable silicide. The corresponding solubilities of the carbon in the stable silicide and in the second metal are sufficiently low that the carbon produced by the silicide reaction forms a graphene layer on the SiC.

Abstract: A process for forming graphene, includes: depositing at least a first and a second metal onto a surface of silicon carbide (SiC), and heating the SiC and the first and second metals under conditions that cause the first metal to react with silicon of the silicon carbide to form carbon and at least one stable silicide. The corresponding solubilities of the carbon in the stable silicide and in the second metal are sufficiently low that the carbon produced by the silicide reaction forms a graphene layer on the SiC.

Abstract: A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.

Abstract: A method for treating a surface of a porous material in an environment is provided, comprising setting the temperature of the surface to a value T1 and setting the pressure of the environment to a value P1, contacting the surface with a fluid having a solidifying temperature at the pressure value P1 above the value T1 and having a vaporizing temperature at the pressure value P1 below 80° C., thereby solidifying the fluid in pores of the material, thereby sealing the pores, treating the surface, wherein the treatment is preferably an etching or a modification of the surface, and setting the temperature of the surface to a value T2 and setting the pressure of the environment to a value P2 in such a way as to vaporize the fluid.

Abstract: A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.

Abstract: A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.

Abstract: Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g.

Abstract: The present invention provides a method for forming a layer (6) of polycrystalline semiconductor material on a substrate (1). The method comprises providing at least one catalyst particle (4) on a substrate (1), the at least one catalyst particle (4) comprising at least a catalyst material, the catalyst material having a melt temperature of between room temperature and 500° C., or being able to form a catalyst material/semiconductor material alloy with a eutectic temperature of between room temperature and 500° C., and forming a layer (6) of polycrystalline semiconductor material on the substrate (1) at temperatures lower than 500° C. by using plasma enhancement of a precursor gas, thereby using the at least one catalyst particle (4) as an initiator. The present invention furthermore provides a layer (6) of polycrystalline semiconductor material obtained by the method according to embodiments of the present invention.

Abstract: The present invention provides a method for forming a layer (6) of polycrystalline semiconductor material on a substrate (1). The method comprises providing at least one catalyst particle (4) on a substrate (1), the at least one catalyst particle (4) comprising at least a catalyst material, the catalyst material having a melt temperature of between room temperature and 500° C., or being able to form a catalyst material/semiconductor material alloy with a eutectic temperature of between room temperature and 500° C., and forming a layer (6) of polycrystalline semiconductor material on the substrate (1) at temperatures lower than 500° C. by using plasma enhancement of a precursor gas, thereby using the at least one catalyst particle (4) as an initiator. The present invention furthermore provides a layer (6) of polycrystalline semiconductor material obtained by the method according to embodiments of the present invention.

Abstract: Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g.

Abstract: A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.

Abstract: A method is provided for making pure-silica-zeolite films useful as low-k material, specifically, more hydrophobic, homogeneous and with absence of cracks. The method utilizes a UV cure; preferably the UV cure is performed at temperatures at higher than the deposition temperature. The UV-assisted cure removes the organic template promoting organic functionalization and silanol condensation, making the silica-zeolite films more hydrophobic. Moreover, the zeolite material is also mechanically stronger and crack-free. The method can be used to prepare pure-silica-zeolite films more suitable as low-k materials in semiconductor processing.

Abstract: A method is provided for making pure-silica-zeolite films useful as low-k material, specifically, more hydrophobic, homogeneous and with absence of cracks. The method utilizes a UV cure; preferably the UV cure is performed at temperatures at higher than the deposition temperature. The UV-assisted cure removes the organic template promoting organic functionalization and silanol condensation, making the silica-zeolite films more hydrophobic. Moreover, the zeolite material is also mechanically stronger and crack-free. The method can be used to prepare pure-silica-zeolite films more suitable as low-k materials in semiconductor processing.

Abstract: Processes for forming a low k dielectric material onto a surface of a substrate comprises depositing the low k dielectric material onto the surface; and exposing the low k dielectric material to ultraviolet radiation for a period of time and intensity effective to increase a mechanical property of the low k dielectric material, wherein the mechanical property is significantly improved compared to a corresponding mechanical property of the low k dielectric material free from exposure to the ultraviolet radiation, or the corresponding mechanical property of the low k dielectric material that is furnace cured, or the corresponding mechanical property of the low k dielectric material that is exposed to excessive activating energy prior to ultraviolet radiation exposure, wherein excessive activating energy comprises an excessive hotplate bake sequence, a furnace cure, an annealing cure, a multi-temperature cure process or plasma treatment prior to the ultraviolet radiation.

Abstract: A method for determining the presence of defects in a covering layer overlying an underlying layer in accordance with an embodiment of the invention comprises providing a substrate comprising the covering layer, where the covering layer is at least partially exposed. The covering layer is subjected to a first substance, such as a solvent, and then subjected to a light beam. An optical property of the covering layer is determined and compared with a threshold value. The presence of defects in the covering layer is determined by the difference of the optical property from the threshold value, where the optical property indicates a level of penetration of the first substance through the covering layer.