Abstract: Parallel binary data from a data source are processed for serialization by circuitry including parallel data registers, a clock ring that provides four phases, and a two phase counter which is operated so that the two phases are in quadrature to each other, and each of its two phases changes count value only once for each complete cycle of the four phase clock ring. The counter has two sets of output signals which are used to select pairs of parallel bits in one of two data registers. The selected bits from the data registers are sampled in serial time by a phase clock pulse from the clock ring, interleaved and processed to form a stream of serialized data bits.