Abstract: The present invention relates to cell radiolabelling agents. The invention provides a method of preparing oxine-containing cell radiolabelling agents, a kit for the preparation of oxine-containing cell radiolabelling agents and a formulation for the preparation of oxine-containing cell radiolabelling agents, in particular 89Zr-oxine cell radiolabelling agents.

Abstract: This application provides a zoom assembly, including a first refraction component and a first lens apparatus. The first refraction component is configured to change a transmission path of light, and the first refraction component includes a first surface, a second surface, a third surface, and a first reflection structure. The three surfaces of the first refraction component are all transmission surfaces. An optical axis of the first lens apparatus is perpendicular to the second surface of the first refraction component. The first reflection structure is attached to the third surface, and is configured to receive light transmitted by one of the transmission surfaces and reflect the light to another transmission surface.

Abstract: Optical cross connects and methods for use therewith are described herein. In an embodiment, an optical cross connect includes first and second mirror arrays, first and second light sources that respectively emit first and second color coded light beams (e.g., each of which includes red, green and blue light), and first and second cameras configured to respectively capture first and second color images of the first and second color coded light beams reflected respectively from the first and second mirror arrays. The optical cross connect also includes a controller configured to perform closed loop feedback control of the first and second mirror arrays, based on the first and second color images, when the controller controls how optical signals are transferred between individual optical fibers in a first bundle of optical fibers and individual optical fibers in a second bundle of optical fibers.

Abstract: A MEMS package includes a cavity formed within a package body, a semiconductor device disposed within the cavity and including a microelectromechanical systems (MEMS) micro-mirror, a damping fluid disposed within the cavity and at least partially surrounding a portion of the MEMS micro-mirror, and a magnet assembly disposed within the cavity and at least partially surrounded by the damping fluid, the magnet assembly being magnetically coupled with the MEMS micro-mirror.

Abstract: Methods and apparatus for reducing the oscillation of a MEMS actuator. In one embodiment, a driving signal is generated to adjust the MEMS actuator through a set of driving wires coupled to the MEMS actuator. A motion-induced signal from the set of driving wires coupled to the MEMS actuator is received in response to the driving signal. The motion-induced signal is filtered to generate a filtered motion-induced signal. The filtered motion-induced signal is amplified to generate an amplified filtered motion-induced signal. The driving signal is adjusted based on the amplified filtered motion-induced signal to reduce the oscillation of the MEMS actuator.

Abstract: Methods and apparatus for reducing the oscillation of a MEMS actuator. In one embodiment, a driving signal is generated to adjust the MEMS actuator through a set of driving wires coupled to the MEMS actuator. A motion-induced signal from the set of driving wires coupled to the MEMS actuator is received in response to the driving signal. The motion-induced signal is filtered to generate a filtered motion-induced signal. The filtered motion-induced signal is amplified to generate an amplified filtered motion-induced signal. The driving signal is adjusted based on the amplified filtered motion-induced signal to reduce the oscillation of the MEMS actuator.

Abstract: Optical cross connects and methods for use therewith are described herein. In an embodiment, an optical cross connect includes first and second mirror arrays, first and second light sources that respectively emit first and second color coded light beams (e.g., each of which includes red, green and blue light), and first and second cameras configured to respectively capture first and second color images of the first and second color coded light beams reflected respectively from the first and second mirror arrays. The optical cross connect also includes a controller configured to perform closed loop feedback control of the first and second mirror arrays, based on the first and second color images, when the controller controls how optical signals are transferred between individual optical fibers in a first bundle of optical fibers and individual optical fibers in a second bundle of optical fibers.

Abstract: A MEMS package includes a cavity formed within a package body, a semiconductor device disposed within the cavity and including a microelectromechanical systems (MEMS) micro-mirror, a damping fluid disposed within the cavity and at least partially surrounding a portion of the MEMS micro-mirror, and a magnet assembly disposed within the cavity and at least partially surrounded by the damping fluid, the magnet assembly being magnetically coupled with the MEMS micro-mirror.

Abstract: A MEMS flow sensor is provided having a micro flow channel etched in a silicon structure composed of two silicon substrates bonded or fused together. A heater and one or more temperature sensors are, in one embodiment, disposed around the perimeter of the flow channel and outside of the channel. In another embodiment, a heater and one or more temperature sensors are respectively disposed outside the flow channel at the top and bottom of the channel. In further embodiments, a heater and one or more temperature sensors are located inside the flow channel on one or more surfaces thereof or around the inside perimeter of the channel. The flow sensors in accordance with the invention are preferably fabricated using wafer scale fabrication techniques.

Abstract: Packaged MEMS devices are described. One such device includes a substrate having an active surface with an integrated circuit. Two substrate pads are formed on the substrate; one pad is a closed ring pad. The device also includes a cap wafer with two wafer pads. One of these wafer pads is also a closed ring pad. A hermetic seal ring is formed by a first bonding between the two ring pads. The device has a gap between the substrate and the cap wafer. This gap may be filled with a pressurized gas. An electrical connection is formed by a second bonding between one substrate pad and one wafer pad. An electrical contact is disposed over the cap wafer. The device also includes an insulation layer between the electrical contact and the cap wafer. Methods of producing the packaged MEMS devices are also described.

Abstract: The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.

Abstract: The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.

Abstract: A MEMS flow sensor is provided having a micro flow channel etched in a silicon structure composed of two silicon substrates bonded or fused together. A heater and one or more temperature sensors are, in one embodiment, disposed around the perimeter of the flow channel and outside of the channel. In another embodiment, a heater and one or more temperature sensors are respectively disposed outside the flow channel at the top and bottom of the channel. In further embodiments, a heater and one or more temperature sensors are located inside the flow channel on one or more surfaces thereof or around the inside perimeter of the channel. The flow sensors in accordance with the invention are preferably fabricated using wafer scale fabrication techniques.

Abstract: Packaged MEMS devices are described. One such device includes a substrate having an active surface with an integrated circuit. Two substrate pads are formed on the substrate; one pad is a closed ring pad. The device also includes a cap wafer with two wafer pads. One of these wafer pads is also a closed ring pad. A hermetic seal ring is formed by a first bonding between the two ring pads. The device has a gap between the substrate and the cap wafer. This gap may be filled with a pressurized gas. An electrical connection is formed by a second bonding between one substrate pad and one wafer pad. An electrical contact is disposed over the cap wafer. The device also includes an insulation layer between the electrical contact and the cap wafer. Methods of producing the packaged MEMS devices are also described.

Abstract: A mask set is described. In one implementation, the mask set includes: a first plurality of base layer masks, where each base layer mask of the first plurality of base layer masks includes a plurality of base layer tiles of a first tile size; a first plurality of top layer masks, where each top layer mask of the first plurality of top layer masks includes a plurality of first top layer tiles of the first tile size; and a second plurality of top layer masks, where each top layer mask of the second plurality of top layer masks includes a plurality of second top layer tiles of a second tile size; where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described.

Abstract: Disclosed herein are methods of preparing and using doped MWNT electrodes, sensors and field-effect transistors. Devices incorporating doped MWNT electrodes, sensors and field-effect transistors are also disclosed.

Abstract: Disclosed herein are methods of preparing and using doped MWNT electrodes, sensors and field-effect transistors. Devices incorporating doped MWNT electrodes, sensors and field-effect transistors are also disclosed.

Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Abstract: A mask set is described. In one implementation, the mask set includes: a first layer mask including a plurality of first tiles of a first tile size; and a second layer mask including a plurality of second tiles of a second tile size, where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described. In one implementation, the method includes: using a first layer mask having a first tile size to fabricate a first layer of a first IC of the plurality of ICs and a first layer of a second IC of the plurality of ICs; and using a second layer mask having a second tile size to fabricate a second layer of the first IC, where the second tile size is different from the first tile size.

Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.