Patents by Inventor Francisco H. De La Moneda

Francisco H. De La Moneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4458406
    Abstract: The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.
    Type: Grant
    Filed: October 9, 1981
    Date of Patent: July 10, 1984
    Assignee: IBM Corporation
    Inventors: Francisco H. De La Moneda, Thomas A. Williams
  • Patent number: 4445267
    Abstract: A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. A first insulating layer such as silicon dioxide which is designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a conductive layer, a second silicon dioxide layer, a first silicon nitride layer, a polycrystalline silicon layer and a second nitride layer are formed thereover. The multilayer structure is etched to result in a patterned polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions.
    Type: Grant
    Filed: December 30, 1981
    Date of Patent: May 1, 1984
    Assignee: International Business Machines Corporation
    Inventors: Francisco H. De La Moneda, Robert C. Dockerty
  • Patent number: 4280855
    Abstract: A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension L.sub.D to the drain. However, the introduction of the depletion extension L.sub.D introduces a manufacturing statistical variation in the characteristics of the resultant devices so produced. The problem of the effects of the variations in the length L.sub.D and thus, variations in the resulting transconductance of the device, is solved by placing two of these devices in parallel. When one device has its L.sub.D relatively shorter, the companion device will also have its L.sub.D correspondingly longer. The method of producing the dual devices is by ion implanting a single conductivity region which forms the L.sub.D for both the left- and right-hand channels for the left- and right-hand DMOS structures. If the mask for the ion-implanted region is misaligned slightly to the right, then the effective L.sub.
    Type: Grant
    Filed: January 23, 1980
    Date of Patent: July 28, 1981
    Assignee: IBM Corporation
    Inventors: Claude L. Bertin, Francisco H. De La Moneda, Donald A. Soderman
  • Patent number: 4149906
    Abstract: A method is disclosed to fabricate a Merged Transistor Logic (MTL) cell having vertical devices with higher beta and f.sub.T, and a lateral device with higher beta than available from conventionally fabricated cells. Features which contribute to these results include a p-type epitaxial layer, highly doped emitter and collector regions for the lateral PNP transistor, a contour for the base region of the lateral PNP which reinforces its transistor action in the bulk rather than at the surface of the epitaxial layer, a highly doped emitter for the vertical device, a uniform doping profile for the base region of the vertical device, dielectric isolation, and the use of heavily doped base regions to reduce injection of emitter current into inactive regions of the cell.
    Type: Grant
    Filed: April 29, 1977
    Date of Patent: April 17, 1979
    Assignee: International Business Machines Corporation
    Inventor: Francisco H. De La Moneda
  • Patent number: 4139935
    Abstract: Protective devices and circuits for insulated gate transistors are improved by another p/n junction diode or MOS diode preventing breakdown of the thin oxide of the protective device. The breakdown voltage of the protective device or p/n diode may be tailored to a preselected voltage by altering its metallurgical junction by ion implantation or other techniques. Tailoring permits the breakdown voltage of the protective device to be independent of process and circuit specification of a protected or internal circuit. A plurality of parallel circuits connected as a protective device limits or controls secondary breakdown of the protective device.
    Type: Grant
    Filed: March 29, 1977
    Date of Patent: February 20, 1979
    Assignee: International Business Machines Corporation
    Inventors: Claude L. Bertin, Francisco H. De La Moneda
  • Patent number: 4138782
    Abstract: An insulated gate field effect transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter.
    Type: Grant
    Filed: November 15, 1977
    Date of Patent: February 13, 1979
    Assignee: International Business Machines Corporation
    Inventors: Francisco H. De la Moneda, Harish N. Kotecha
  • Patent number: 4115794
    Abstract: An improved charge pumping device is disclosed for charge storage memory elements and substrate bias control. By selectively ion-implanting the substrate of the charge pump, its output current is substantially increased and its losses by charge dissipation are reduced. Charge pumps are used to charge a substrate-series capacitor combination to a desired bias point. In the substrate bias application, by integrating the series capacitor with the charge pump on the semiconductor chip and making the capacitor an integral part of a low resistance conductive blanket implant, the voltage regulation of the biasing circuit is improved.
    Type: Grant
    Filed: December 16, 1977
    Date of Patent: September 19, 1978
    Assignee: International Business Machines Corporation
    Inventor: Francisco H. De La Moneda
  • Patent number: 4102733
    Abstract: Semiconductor wafer processes employing two and three masks are disclosed for fabricating a plurality of insulated gate field effect transistors (IGFETs) to be used singly as discrete devices or interconnected as integrated circuits on the wafer by means of diffused regions at a first level and a composite of polysilicon and metal silicide layers at a second level. The first mask of the two-mask process is used in opening windows through a thick oxide layer covering the wafer for the gate and diffused regions including the source and drain regions. After forming a thin oxide layer in these windows, the wafer is coated with successive layers of polysilicon and silicon nitride. Then, a second masking operation yields a pattern out of the polysilicon-nitride layer including gate electrodes and a top-lying interconnection level which abuts to openings etched through the thin oxide layer. Doping impurities are diffused therethrough to form source and drain regions and crossunders.
    Type: Grant
    Filed: April 29, 1977
    Date of Patent: July 25, 1978
    Assignee: International Business Machines Corporation
    Inventors: Francisco H. De La Moneda, Harish N. Kotecha
  • Patent number: 4102714
    Abstract: A structure and process are disclosed for making a low-voltage breakdown p-n junction in a semiconductor substrate. The process comprises the step of etching a V-shaped groove in a semiconductor substrate of a first conductivity type, with an anistropic etchant, followed by depositing a layer of epitaxial semiconductor material of a second conductivity type in the V-shaped groove. There results a p-n junction with a small radius of curvature at the apex of the V-shaped groove having a correspondingly low breakdown voltage.
    Type: Grant
    Filed: April 23, 1976
    Date of Patent: July 25, 1978
    Assignee: International Business Machines Corporation
    Inventors: David E. DeBar, Francisco H. De La Moneda
  • Patent number: 4078243
    Abstract: Variations of current gain from element to element in a phototransistor array are eliminated by covering the array with an opaque mask and etching openings in the mask over each phototransistor based upon an area reduction factor (ARF). The area reduction factor for an opening is equal to (I.sub.m /I.sub.x).sup.1-n where n is a constant definitive of the change in beta of a phototransistor in the array over a given range of collector currents; I.sub.m is the minimum collector current measured for the array and I.sub.x is the collector current for the phototransistor beneath the opening. Based upon the ARF's, the openings etched in the mask or cover initiate uniform current from each phototransistor element when uniform light flux is directed on the array.
    Type: Grant
    Filed: December 12, 1975
    Date of Patent: March 7, 1978
    Assignee: International Business Machines Corporation
    Inventors: David E. De Bar, Francisco H. De La Moneda
  • Patent number: 4072868
    Abstract: An insulated Gate Field Effect Transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter.
    Type: Grant
    Filed: September 16, 1976
    Date of Patent: February 7, 1978
    Assignee: International Business Machines Corporation
    Inventors: Francisco H. De La Moneda, Harish N. Kotecha
  • Patent number: 4072545
    Abstract: Disclosed is an integrated circuit field effect transistor having a source and drain which protrude above the silicon substrate so as to create shallow junctions with the substrate while maintaining a relatively low sheet resistivity in the region. Two self-aligned source and drain fabrication processes are disclosed for the device. The first process yields a polysilicon field shield and the second process yields a field region composed of thermal silicon dioxide.
    Type: Grant
    Filed: May 21, 1976
    Date of Patent: February 7, 1978
    Assignee: International Business Machines Corp.
    Inventor: Francisco H. De La Moneda
  • Patent number: 4029522
    Abstract: A method is disclosed to implant layers in semiconductor substrates with asymmetrical edges, that is, one edge slopes towards the surface of the substrate and the other terminates abruptly inside the bulk. The method involves using lift-off techniques to make ion-stopping masks with near-vertical sidewalls which delineate the abrupt edges of the ion-implanted layers. The application of this method to fabricate Schottky barrier FET's and bipolar transistors yields devices with reduced parasitic resistance without adversely impacting other related electrical parameters such as breakdown voltage and capacitance.
    Type: Grant
    Filed: June 30, 1976
    Date of Patent: June 14, 1977
    Assignee: International Business Machines Corporation
    Inventor: Francisco H. De La Moneda
  • Patent number: 4016587
    Abstract: Disclosed is an integrated circuit field effect transistor having a source and drain which protrude above the silicon substrate so as to create shallow junctions with the substrate while maintaining a relatively low sheet resistivity in the region. Two self-aligned source and drain fabrication processes are disclosed for the device. The first process yields a polysilicon field shield and the second process yields a field region composed of thermal silicon dioxide.
    Type: Grant
    Filed: December 3, 1974
    Date of Patent: April 5, 1977
    Assignee: International Business Machines Corporation
    Inventor: Francisco H. De La Moneda
  • Patent number: 3958323
    Abstract: A process is disclosed for making a self-aligned IGFET having a polycrystalline silicon gate, using three masking steps. Layers of silicon dioxide, polycrystalline silicon, and silicon nitride are respectively deposited on the surface of a silicon substrate of a first conductivity type. With the first mask, openings are made in regions of these layers above the proposed location for the source and drain. The source and drain are then deposited in the substrate through these openings. The disclosed process continues, growing a silicon dioxide layer on the lateral surfaces of the polysilicon gate, exposed by these openings. Then a silicon nitride layer is deposited on all exposed surfaces and a second mask is employed to permit the removal by etching of this nitride layer from all portions except the proposed location of devices metallization at a first region over the gate, a second region over the source and a third region over the drain of the device.
    Type: Grant
    Filed: April 29, 1975
    Date of Patent: May 25, 1976
    Assignee: International Business Machines Corporation
    Inventor: Francisco H. De La Moneda