Patents by Inventor Franciscus van der Goes

Franciscus van der Goes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9985671
    Abstract: A device includes circuitry configured to detect one or more properties of an image signal based on outputs from one or more (analog-to-digital converter) ADC configurations of a transceiver, determine a VCO frequency corresponding to an ADC sampling frequency independently from a carrier frequency, and control the VCO frequency of at least one of a transmitter or receiver based on the one or more properties of the image signal.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 29, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: David C. Garrett, Franciscus Van Der Goes, Hooman Darabi, Ramon A. Gomez
  • Publication number: 20170207800
    Abstract: A device includes circuitry configured to implement one or more PHY communications protocols to simultaneously communicate with one or more stations via communication links on one or more wireless networks, communicate with additional devices via a backhaul network, and exchange collaboration data, including at least one of protocol data or collaborative beamforming data, with the additional devices via the backhaul network to maintain signal parameters of communications signals with the one or more stations.
    Type: Application
    Filed: February 12, 2016
    Publication date: July 20, 2017
    Applicant: BROADCOM CORPORATION
    Inventors: David C. GARRETT, Franciscus VAN DER GOES, Hooman DARABI, Ramon A. GOMEZ, Murat MESE
  • Publication number: 20170207803
    Abstract: A device includes circuitry configured to detect one or more properties of an image signal based on outputs from one or more (analog-to-digital converter) ADC configurations of a transceiver, determine a VCO frequency corresponding to an ADC sampling frequency independently from a carrier frequency, and control the VCO frequency of at least one of a transmitter or receiver based on the one or more properties of the image signal.
    Type: Application
    Filed: February 12, 2016
    Publication date: July 20, 2017
    Applicant: AVAGO TECHNOLOGIES GERNERAL IP (SINGAPORE) PTE. LTD.
    Inventors: David C. GARRETT, Franciscus Van Der Goes, Hooman Darabi, Ramon A. Gomez
  • Publication number: 20170207935
    Abstract: A device includes circuitry configured to determine noise shaping parameters for one or more transmit signals on one or more transmit channels based on transmission protocol and spectral mask criteria. Frequency positions are identified for the one or more transmit channels based on the noise shaping parameters, and the noise shaping parameters are applied to the one or more transmit signals.
    Type: Application
    Filed: February 12, 2016
    Publication date: July 20, 2017
    Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: David C. GARRETT, Franciscus Van Der Goes, Hooman Darabi, Ramon A. Gomez, Murat Mese
  • Patent number: 9712348
    Abstract: A device includes circuitry configured to determine noise shaping parameters for one or more transmit signals on one or more transmit channels based on transmission protocol and spectral mask criteria. Frequency positions are identified for the one or more transmit channels based on the noise shaping parameters, and the noise shaping parameters are applied to the one or more transmit signals.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 18, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: David C. Garrett, Franciscus Van Der Goes, Hooman Darabi, Ramon A. Gomez, Murat Mese
  • Patent number: 9660670
    Abstract: A device includes circuitry configured to assess a broadband spectrum environment including signal and blocker characteristics via one or more receiver paths, determine operational parameters for the device based on the signal and blocker characteristics, and align one or more radio components from one or more radios for operation based on the operational parameters of the device.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 23, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: David C. Garrett, Franciscus Van Der Goes, Hooman Darabi, Ramon A. Gomez
  • Patent number: 9325313
    Abstract: A low-power level-shift circuit for data-dependent signals includes a buffer circuit, a coupling capacitor, and a biasing circuit. The buffer circuit is biased by a low-voltage domain voltage supply and configured to receive a data-dependent signal. The coupling capacitor is coupled, at a first node, to an output node of the buffer circuit. The biasing circuit is coupled to a second node of the coupling capacitor and a switch. The level-shift circuit can translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 26, 2016
    Assignee: Broadcom Corporation
    Inventors: Franciscus Van Der Goes, Christopher Michael Ward
  • Publication number: 20150214946
    Abstract: A low-power level-shift circuit for data-dependent signals includes a buffer circuit, a coupling capacitor, and a biasing circuit. The buffer circuit is biased by a low-voltage domain voltage supply and configured to receive a data-dependent signal. The coupling capacitor is coupled, at a first node, to an output node of the buffer circuit. The biasing circuit is coupled to a second node of the coupling capacitor and a switch. The level-shift circuit can translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch.
    Type: Application
    Filed: February 20, 2014
    Publication date: July 30, 2015
    Applicant: BROADCOM CORPORATION
    Inventors: Franciscus VAN DER GOES, Christopher Michael WARD
  • Publication number: 20080088493
    Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
    Type: Application
    Filed: September 18, 2007
    Publication date: April 17, 2008
    Applicant: Broadcom Corporation
    Inventors: Jan MULDER, Franciscus van der GOES, Jan WESTRA, Rudy van der PLASSCHE
  • Publication number: 20070257744
    Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.
    Type: Application
    Filed: July 9, 2007
    Publication date: November 8, 2007
    Applicant: Broadcom Corporation
    Inventors: Jan Westra, Jan Mulder, Franciscus van der Goes
  • Publication number: 20070176664
    Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 2, 2007
    Applicant: Broadcom Corporation
    Inventors: Ovidiu Bajdechi, Franciscus van der Goes
  • Publication number: 20060164126
    Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 27, 2006
    Inventors: Jan Mulder, Franciscus van der Goes, Marcel Lugthart
  • Publication number: 20050162195
    Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
    Type: Application
    Filed: March 24, 2005
    Publication date: July 28, 2005
    Inventors: Jan Mulder, Franciscus van der Goes
  • Publication number: 20050093644
    Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.
    Type: Application
    Filed: April 23, 2004
    Publication date: May 5, 2005
    Applicant: Broadcom Corporation
    Inventors: Jan Westra, Jan Mulder, Franciscus van der Goes