Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.

Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.

Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.

Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.

Abstract: A method for fabricating patterns of III-V semiconductor material on a semiconductor substrate based on oriented silicon or germanium comprises: production of a growth mask on the surface of the substrate, defining masking patterns Miox of width L, of height hox with a distance S between masking patterns; growth of patterns MiIII-V of III-V material between said masking patterns, such that said patterns exhibit a height h relative to the top plane of said masking patterns, said height h being at or above a critical minimum height hc, the growth step comprising: determining growth rates v100 and v110 at right angles to the face of the III-V material, defining ratio R=v100/v110; determining the angle of dislocations ? of the III-V material relative to the plane of the substrate; determining the critical minimum height hc by the equation: h c = h ox - S × tan ? ( ? ) tan ? ( ? ) R - 1 with R being determined to be greater than tan(?).

Abstract: A method for fabricating patterns of III-V semiconductor material on a semiconductor substrate based on oriented silicon or germanium comprises: production of a growth mask on the surface of the substrate, defining masking patterns Miox of width L, of height hox with a distance S between masking patterns; growth of patterns MiIII-V of III-V material between said masking patterns, such that said patterns exhibit a height h relative to the top plane of said masking patterns, said height h being at or above a critical minimum height hc, the growth step comprising: determining growth rates v100 and v110 at right angles to the face of the III-V material, defining ratio R=v100/v110; determining the angle of dislocations ? of the III-V material relative to the plane of the substrate; determining the critical minimum height hc by the equation: h c = h ox - S × tan ? ( ? ) tan ? ( ? ) R - 1 with R being determined to be greater than tan(?).