Patents by Inventor Francky Catthoor

Francky Catthoor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11847944
    Abstract: A system and for distributing data for 3D light field projection and a method thereof. The system comprises input terminals and output terminals that are connectable to pixel elements of a display. Data paths are established between input terminals and output terminals, and are controlled by data switches. The system also comprises a control plane adapted for applying control variables to the data switches. Control switches of the control plane select the control variables which are applied to the data switches. Sequences of control variables and enable variables propagate along at least one first delay line and along at least one second delay line, respectively. Delay units of the at least one first delay line and of the at least one second delay line have a synchronous relationship. During system run-time patterns contained in the stream of input data are detected for determining the sequences of control variables.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 19, 2023
    Assignee: IMEC VZW
    Inventors: Francky Catthoor, Jan Genoe, Xavier Rottenberg
  • Patent number: 11704462
    Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 18, 2023
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Pieter Weckx, Dimitrios Rodopoulos, Benjamin Kaczer, Francky Catthoor
  • Patent number: 11677401
    Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: June 13, 2023
    Assignee: IMEC VZW
    Inventors: Francky Catthoor, Edouard Giacomin, Juergen Boemmels, Julien Ryckaert
  • Publication number: 20230179315
    Abstract: Example embodiments relate to methods for disseminating scaling information and applications thereof in very large scale integration (VLSI) implementations of fixed-point fast Fourier transforms (FFTs). One embodiment includes a method for disseminating scaling information in a system. The system includes a linear decomposable transformation process and an inverse process of the linear decomposable transformation process. The inverse process of the linear decomposable transformation process is defined, in time or space, as an inverse linear decomposable transformation process. The linear decomposable transformation process is separated from the inverse linear decomposable transformation process. The linear decomposable transformation process or the inverse linear decomposable transformation process is able to be performed first and is defined as a linear decomposable transformation I. The other remaining process is performed subsequently and is defined as a linear decomposable transformation II.
    Type: Application
    Filed: October 26, 2022
    Publication date: June 8, 2023
    Inventors: Xinzhe Liu, Raees Kizhakkumkara Muhamad, Dessislava Nikolova, Yajun Ha, Francky Catthoor, Fupeng Chen, Peter Schelkens, David Blinder
  • Patent number: 11537091
    Abstract: A localized smart energy management system comprises a plurality of controllable loads, at least one intermittent energy source, a selectively connectable dispatchable energy source, and optionally an energy storage system. A method for balancing power production and power consumption of such localized smart energy management systems in real time comprises performing a coarse-grained optimization in a first layer of a hierarchical optimization structure to generate a predicted schedule, based on long-term load demand profiles and long-term power generation profiles. A second layer iteratively refines the predicted schedule upon receiving a new forecast of a short-term power generation profile for the at least one intermittent energy source.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 27, 2022
    Assignee: IMEC VZW
    Inventors: Johannes Goverde, Francky Catthoor, Ittetsu Taniguchi, Patrizio Manganiello, Daichi Watari
  • Patent number: 11475101
    Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 18, 2022
    Assignee: Imec VZW
    Inventors: Francky Catthoor, Praveen Raghavan, Dimitrios Rodopoulos, Mohit Dandekar
  • Publication number: 20220271755
    Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell
    Type: Application
    Filed: May 10, 2022
    Publication date: August 25, 2022
    Inventors: Francky CATTHOOR, Edouard GIACOMIN, Juergen BOEMMELS, Julien RYCKAERT
  • Patent number: 11381242
    Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: July 5, 2022
    Assignee: IMEC VZW
    Inventors: Francky Catthoor, Edouard Giacomin, Juergen Boemmels, Julien Ryckaert
  • Publication number: 20220109447
    Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell
    Type: Application
    Filed: October 5, 2020
    Publication date: April 7, 2022
    Inventors: Francky CATTHOOR, Edouard GIACOMIN, Juergen BOEMMELS, Julien RYCKAERT
  • Publication number: 20220100941
    Abstract: The present disclosure relates to a memory device comprising a memory array and a periphery circuitry configured to read data from and/or write data to the memory array, wherein the periphery circuitry comprises a programmable circuitry causing the memory device to access data stored in the memory array in accordance with manifest loop instructions. The programmable circuitry comprises a control logic configured to control the operation of the periphery circuitry in accordance with a set of parameters derived from the manifest loop instructions. The present disclosure further relates to a method for controlling the operation of a memory device and to a processing system comprising the memory device.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 31, 2022
    Inventors: Francky Catthoor, Jan Stuijt, Sandeep Pande
  • Publication number: 20220100939
    Abstract: A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Subrat Mishra, Pieter Weckx, Francky Catthoor, Alessio Spessot
  • Publication number: 20210247720
    Abstract: A system and for distributing data for 3D light field projection and a method thereof. The system comprises input terminals and output terminals that are connectable to pixel elements of a display. Data paths are established between input terminals and output terminals, and are controlled by data switches. The system also comprises a control plane adapted for applying control variables to the data switches. Control switches of the control plane select the control variables which are applied to the data switches. Sequences of control variables and enable variables propagate along at least one first delay line and along at least one second delay line respectively. Delay units of the at least one first delay line and of the at least one second delay line have a synchronous relationship. During system run-time patterns contained in the stream of input data are detected for determining the sequences of control variables.
    Type: Application
    Filed: June 3, 2019
    Publication date: August 12, 2021
    Inventors: Francky Catthoor, Jan Genoe, Xavier Rottenberg
  • Patent number: 10963603
    Abstract: A method for generating/updating a database of current-voltage characteristic curves is disclosed. This method includes simulating for at least one combination of a topology of a photovoltaic cell group, an internal cell temperature(s) and a cell irradiation(s), a model of the photovoltaic cell group to provide a representative current-voltage characteristic curve, and clustering the current-voltage characteristic curves to identify at least one plurality of similar current-voltage characteristic curves.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 30, 2021
    Assignees: Imec vzw, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Francky Catthoor, Maria-Iro Baka, Patrizio Manganiello
  • Patent number: 10956993
    Abstract: A computer-implemented method and related device are disclosed for determining a plurality of operating scenarios of an energy system. The method comprises obtaining a plurality of performance measures of the energy system as a function of time corresponding to a plurality of sets of values of input variables. The method comprises clustering the plurality of sets of values of the input variables and the performance measures associated therewith into groups and defining a descriptor for each of the groups. The method also comprises outputting the descriptors of the groups for use in an online prediction or offline estimation of the energy system.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 23, 2021
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Dimitrios Anagnostos, Francky Catthoor, Johannes Goverde
  • Publication number: 20210011439
    Abstract: A localized smart energy management system comprises a plurality of controllable loads, at least one intermittent energy source, a selectively connectable dispatchable energy source, and optionally an energy storage system. A method for balancing power production and power consumption of such localized smart energy management systems in real time comprises performing a coarse-grained optimization in a first layer of a hierarchical optimization structure to generate a predicted schedule, based on long-term load demand profiles and long-term power generation profiles. A second layer iteratively refines the predicted schedule upon receiving a new forecast of a short-term power generation profile for the at least one intermittent energy source.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 14, 2021
    Inventors: Johannes Goverde, Francky Catthoor, Ittetsu Taniguchi, Patrizio Manganiello, Daichi Watari
  • Patent number: 10802743
    Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 13, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Francky Catthoor, Praveen Raghavan, Daniele Garbin, Dimitrios Rodopoulos, Odysseas Zografos
  • Patent number: 10732350
    Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over ? with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 4, 2020
    Assignees: IMEC vzw, Katholiek Universiteit Leuven
    Inventors: Odysseas Zografos, Francky Catthoor, Sourav Dutta, Azad Naeemi
  • Publication number: 20200159809
    Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Inventors: Francky Catthoor, Praveen Raghavan, Dimitrios Rodopoulos, Mohit Dandekar
  • Patent number: 10651787
    Abstract: The present disclosure relates to reconfigurable voltaic modules. One example embodiment includes a photovoltaic module. The photovoltaic module includes a plurality of photovoltaic cells arranged in a grid having logical rows and columns. The photovoltaic module also includes a plurality of non-reconfigurable interconnects electrically interconnecting subsets of the plurality of photovoltaic cells to form a plurality of cell strings. In addition, the photovoltaic module includes a plurality of reconfigurable interconnects. Each cell string includes at least four photovoltaic cells connected in an electrical series from a first cell to a last cell, the first cell and the last cell being located on a same edge of the grid.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 12, 2020
    Assignee: IMEC VZW
    Inventors: Francky Catthoor, Maria-Iro Baka
  • Publication number: 20200089829
    Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.
    Type: Application
    Filed: July 25, 2019
    Publication date: March 19, 2020
    Inventors: Pieter Weckx, Dmitrios Rodopoulos, Benjamin Kaczer, Francky Catthoor