Abstract: An over-current protection circuit for composite transistor devices is provided, connected between an input terminal and a load, and including: a control-terminal voltage-generation module whose output voltage varies with its input voltage when driven by a first voltage, wherein the output voltage of the control-terminal voltage-generation module serves as a control-terminal voltage; a composite transistor device, connected between the control-terminal voltage-generation module and the load, configured to conduct in response to the control-terminal voltage and a second voltage to generate an output current flowing through the load; and an over-current protection module, connected between the composite transistor device and the load, wherein when the output current of the composite transistor device exceeds a preset limit, a clamping voltage is applied to the composite transistor device by the over-current protection module to limit a current flowing through the composite transistor device, thereby limiting th

Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

Abstract: A converter includes a first switch coupled between a first input terminal and a first terminal of an inductor, and a second switch coupled between a second terminal of the inductor and a second input terminal. A third switch is coupled between the second terminal of the inductor and a first output terminal, and a fourth switch is coupled between the first terminal of the inductor and a second output terminal. A capacitor is coupled between the first and second output terminals. A control circuit monitors a regulated voltage between the first and second output terminals. During a charge phase, the first and second switches are closed to charge the inductor. During a discharge phase, the third and fourth switches are closed to charge the capacitor and increase the regulated voltage.

Abstract: An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1st order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.

Abstract: A converter includes a first switch coupled between a first input terminal and a first terminal of an inductor, and a second switch coupled between a second terminal of the inductor and a second input terminal. A third switch is coupled between the second terminal of the inductor and a first output terminal, and a fourth switch is coupled between the first terminal of the inductor and a second output terminal. A capacitor is coupled between the first and second output terminals. A control circuit monitors a regulated voltage between the first and second output terminals. During a charge phase, the first and second switches are closed to charge the inductor. During a discharge phase, the third and fourth switches are closed to charge the capacitor and increase the regulated voltage.

Abstract: A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.

Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.

Abstract: A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Abstract: The present invention provides a pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) circuit with decoupled flip-around MDAC, capacitive attenuation solution and self-embedded offset cancellation. The flip-around MDAC architecture is built for low inter-stage gain implementation. A capacitive attenuation solution is provided for minimizing the power dissipation and optimizing conversion speed. The design reuses SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time.

Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.

Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Abstract: The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

Abstract: The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

Abstract: The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic.

Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.

Abstract: A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator.

Abstract: A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator.

Abstract: A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.