Abstract: An image sensor provided with a pixel including a photosensitive region formed in a semiconductor substrate and surrounded by a peripheral isolation trench; a sense node formed on a charge collecting region; a charge transfer gate around the sense node; a well; the pixel being provided with a so-called “detection acceleration” transistor configured to, during a so-called “charge overflow detection” operation, be switched on so as to weaken a potential barrier generated by the transfer gate and thus to favour an overflow of photogenerated charges to the sense node of the photosensitive region and to accelerate detection of this overflow.

Abstract: The present disclosure relates to a light sensor (4), wherein each of its pixels comprises: first and second MOS transistors (T1, T2) series-connected through their sources (S), a gate of the second transistor (T2) receiving a comparative voltage (Vcmp); a first current source (104) series-connected with said transistors (T1, T2) between a first supply voltage (GND) and a second supply voltage (VDD2); a third MOS transistor (T3) and a second current source (108) series-connected between a third supply voltage (GND) and a fourth supply voltage (VDD1), wherein the third transistor (T3) has a gate connected to a connection node (106) of the first current source (104) to the first and second transistors (T1, T2); a photodiode (PD) coupled to a gate of the first transistor (T1); and a switch (RST) connected to the gate of the first transistor (T1).

Abstract: The present description concerns a pixel array comprising one or a plurality of pixels (PIX1). Each pixel comprises a first transistor having its control node coupled to a photodiode, a first main conduction node coupled to a first output voltage rail (VS), and a second main conduction node coupled to a second voltage rail (VCS). The array comprises a variable impedance (404) coupling the first voltage rail (VS) to a first power supply rail (VDD) and a current source (402) coupling the second voltage rail (VCS) to a second power supply rail (GND), the variable impedance (404) being controlled based on a voltage on the second voltage rail (VCS). The array comprises a first switch (4002) coupling the second voltage rail (VCS) to a third voltage rail (VINIT1).

Abstract: The present description concerns a photosite including: a photoconversion area configured to convert light into charges; at least one assembly of a first node and of a first charge flow path including a first switch configured to allow the flowing of charges from the photoconversion area to the first node of said assembly when said first switch is on and block the passage of charges between the photoconversion area and the first node of said assembly when said first switch is off; and a second charge flow path between said photoconversion area and a second node of the photosite, wherein the first and second paths are configured so that each first path holds the priority over the second path when the first switch of said first path is on.

Abstract: An image sensor including: a pixel circuit comprising a first transistor having one of its main conducting nodes connected to an output line, the other of its main conducting nodes coupled to a supply voltage rail via a read transistor, and its control node coupled to a sense node of the pixel circuit; a current source coupled to the output line; and a control circuit configured to read a pixel voltage from the pixel circuit by: activating the current source while the read transistor is non-conducting; and deactivating the current source and activating the read transistor of the pixel circuit in order to impose a boosted voltage at the sense node.

Abstract: A pixel array including a first pixel having a first transistor having: its control node coupled to a first photodiode; a first of its main conducting nodes coupled to a voltage output rail; and a second of its main conducting nodes coupled to a further voltage rail; a variable impedance coupling the voltage output rail to a first supply rail of the pixel array; and a current source coupling the further voltage rail to a second supply rail of the pixel array, wherein the variable impedance is controlled based on the voltage level on the further voltage rail.

Abstract: The invention provides an image sensor comprising a light receiving side (Fa) and, in a substrate (100), a photoelectric conversion region (PD) capable of converting light received from the light receiving side (Fa) into a charge, a storage region (SN) capable of storing a charge transferred from the photoelectric conversion region and an optical isolation element of the storage region. The optical isolation element (60) is buried in the substrate between the light receiving side and the storage region.

Abstract: A device of acquisition of a depth image of a scene by detection of a reflected light signal. The device includes a stack of a first sensor and of a second sensor. The first sensor includes first depth photosites configured to acquire at least one first sample of charges photogenerated during first time periods. The second sensor includes second depth photosites arranged opposite the first photosites, the second photosites being configured to acquire at least one second sample of charges photogenerated during second time periods offset with respect to the first time periods by a first constant phase shift. The first sensor or the second sensor further includes third photosites configured to acquire at least one third sample during third time periods offset with respect to the first time periods by a second constant phase shift.

Abstract: A device of acquisition of a depth image and of a 2D image of a scene, including depth photosites and capacitors, each depth photosite including a photodiode capable of detecting a reflected light signal, and at least one sense node coupled to the photodiode by a single transistor. Each capacitor is connected between the sense nodes of two photosites or between two sense nodes of a same photosite. Depth photosites supply the first plate of each capacitor with at least one first sample of charges photogenerated during first time periods, and supplying the second plate of each capacitor with a second sample of charges photogenerated during second time periods. Depth photosites supply the first plate of each capacitor with at least one third sample of charges photogenerated during third time periods.

Abstract: A SPAD-type photodiode comprising a depletion area in a first portion of a semiconductor substrate of a first conductivity type and further comprising a gate electrically-insulated from the substrate, extending into the substrate from an upper surface of the substrate, and separating the first portion of the substrate from a second portion. The photodiode further comprises a first region of the second conductivity type extending from the upper surface of the substrate into the second portion.

Abstract: An image sensor comprising a plurality of pixels formed inside and on top of a semiconductor substrate, each pixel comprising: a photosensitive area formed in the semiconductor substrate; a storage area formed in the semiconductor substrate; and a first transistor of transfer between the photosensitive area and the storage area, wherein the first transfer transistor comprises a gate vertically extending in the semiconductor substrate, from a top surface of the semiconductor substrate, inside of an insulating trench delimiting the storage area.

Abstract: The present disclosure concerns a SPAD photodiode control circuit, including: a first current source; a current mirror including an input transistor in series with the first current source and an output transistor in series with the SPAD photodiode and a second current source in series with the input transistor of the current mirror and in parallel with the first current source, the second current source being alternately controllable to a so-called inactive state where it delivers no current and to a so-called active state where it delivers a non-zero current which adds, in the input transistor of the current mirror, to a current delivered by the first current source.

Abstract: An image sensor including: a pixel circuit comprising a first transistor having one of its main conducting nodes connected to an output line, the other of its main conducting nodes coupled to a supply voltage rail via a read transistor, and its control node coupled to a sense node of the pixel circuit; a current source coupled to the output line; and a control circuit configured to read a pixel voltage from the pixel circuit by: activating the current source while the read transistor is non-conducting; and deactivating the current source and activating the read transistor of the pixel circuit in order to impose a boosted voltage at the sense node.

Abstract: A pixel array including a first pixel having a first transistor having: its control node coupled to a first photodiode; a first of its main conducting nodes coupled to a voltage output rail; and a second of its main conducting nodes coupled to a further voltage rail; a variable impedance coupling the voltage output rail to a first supply rail of the pixel array; and a current source coupling the further voltage rail to a second supply rail of the pixel array, wherein the variable impedance is controlled based on the voltage level on the further voltage rail.

Abstract: A circuit for controlling a first field-effect transistor of a power converter, intended for a converter including at least one first and one second transistor connected in series between two terminals for applying a first voltage, the circuit including a circuit for detecting the opening of the second transistor.

Abstract: A circuit for generating a negative voltage on the basis of a positive voltage, including: at least one first transistor between a first terminal for applying a potential greater than a reference potential and a first node; a first capacitive element between the first node and a second node, a control terminal of said first transistor being linked to the second node; a first switch between the first node and a second terminal for applying the reference potential; a second switch between the second node and a third terminal for providing said negative voltage; a third switch between the second node and the second terminal; and a second capacitive element between the third terminal and the second terminal.

Abstract: An optoelectronic circuit including a full-wave rectifier circuit including light-emitting diodes and a circuit limiting the current passing through the light-emitting diodes.

Abstract: A circuit for controlling a first field-effect transistor of a power converter, intended for a converter including at least one first and one second transistor connected in series between two terminals for applying a first voltage, the circuit including a circuit for detecting the opening of the second transistor.

Abstract: A circuit for generating a negative voltage on the basis of a positive voltage, including: at least one first transistor between a first terminal for applying a potential greater than a reference potential and a first node; a first capacitive element between the first node and a second node, a control terminal of said first transistor being linked to the second node; a first switch between the first node and a second terminal for applying the reference potential; a second switch between the second node and a third terminal for providing said negative voltage; a third switch between the second node and the second terminal; and a second capacitive element between the third terminal and the second terminal.

Abstract: The invention relates to liquid crystal matrix micro displays, and in particular those which are embodied on a monolithic silicon substrate in which are integrated the electronic circuits for control of a matrix array of liquid crystal cells. The matrix comprises, for each dot at the crossover of a row and of a column, an elementary electronic circuit for controlling an elementary liquid crystal cell situated at this crossover. This circuit comprises at least one storage capacitor for storing for the duration of an image frame an analogue voltage applied by the column, a first terminal of the storage capacitor being linked to the gate of the transistor, and, in series between two voltage supply terminals, an elementary current source and a switching transistor, the drain of the switching transistor being linked to the liquid crystal cell. A periodic voltage ramp, common to all the cells of at least one row, is applied to a second terminal of the storage capacitor of the cells of this row.