Patents by Inventor Frank A. Montegari

Frank A. Montegari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5465230
    Abstract: A read/write/restore circuit is disclosed for use in a memory array such as a static RAM array. The circuit employs data and data-complement signals having three states in combination with a two-state address signal to perform read, write and restore functions for the array, to reduce the number of components and control lines needed. The circuit is preferably implemented in BICMOS technology.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: November 7, 1995
    Assignee: International Business Machines Corporation
    Inventor: Frank A. Montegari
  • Patent number: 5331216
    Abstract: A high speed bipolar multiplexer circuit adds less than ten picoseconds delay to the data or test paths. The multiplexer circuit incorporates a low gain linear amplifier which is completely stable and compensates for any level losses through the input emitter followers. The minimal delay introduced in the system data paths and the good isolation between system data inputs and test data inputs matches the performance of the logic and memory circuits of the chips in which multiplexer circuits are incorporated.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: July 19, 1994
    Assignee: International Business Machines Corporation
    Inventors: Walter S. Klara, Frank A. Montegari, Gordon S. Sager
  • Patent number: 5283481
    Abstract: A decoder implemented using bifet technology to exhibit high performance, high density, and low power dissipation. The decoder has multiple input lines for conducting signals at ECL-compatible voltage levels and an output line for conducting signals at CMOS-compatible voltage levels. The output line is enabled in response to a predetermined combination of ECL-compatible voltage level signals on said input lines. The decoder comprises a gate for generating an OR output at ECL-compatible voltage levels according to the input line signals. An inverter is coupled to the OR gate for inverting and amplifying the OR output to produce an inverted output at CMOS voltage levels. A word line driver is coupled to an output of the inverter for isolating and driving the output line according to the inverted output. Finally, power saving means are coupled to the inverter for minimizing power dissipation in the decoder.
    Type: Grant
    Filed: December 26, 1990
    Date of Patent: February 1, 1994
    Assignee: International Business Machines Corporation
    Inventors: Vilnis Klimanis, Frank A. Montegari
  • Patent number: 5276363
    Abstract: A zero power decoder/driver circuit for high performance array chips dissipates zero power when in the deselected state. The decoder/driver circuit is a complementary bipolar circuit comprising a first bipolar transistor of a first conductivity type having its base connected to a down level decoded output of a first level decoder and its emitter connected to an up level decoded output of said first level decoder. The decoder/driver circuit is selected by a predetermined voltage differential across the base/emitter circuit of the first transistor. A diode-connected second bipolar transistor of a second conductivity type is connected to the collector of said first bipolar transistor. A line driver third bipolar transistor of the second conductivity type is connected to a load resistor and mirrors current flowing in said second bipolar transistor.
    Type: Grant
    Filed: August 13, 1992
    Date of Patent: January 4, 1994
    Assignee: International Business Machines Corporation
    Inventors: Walter S. Klara, Frank A. Montegari
  • Patent number: 5257227
    Abstract: A circuit for accessing a column of memory cells in an array of memory cells includes a pair of drivers for activating bit lines for writing data into a selected cell in the column of cells. Each driver includes a bipolar transistor operated with current and voltage applied to a base terminal thereof by a pair of field-effect transistors (FETs) wherein one of the transistors effectively shorts the base terminal to an emitter terminal for elimination of current flow during a state of nonconduction, this FET being overridden by a second FET which applies base current during a state of conduction during writing of the cell. The second FET in each driver is activated by a column address signal applied to a drain terminal thereof, and by a data input signal applied to a gate terminal of the FET to provide for writing during concurrence of the two signals.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: October 26, 1993
    Assignee: International Business Machines Corp.
    Inventors: Vilnis Klimanis, Frank A. Montegari
  • Patent number: 5172010
    Abstract: A chopper/stretcher circuit provides on-chip clock distribution with minimum insertion delay. The on-chip clock chopper/stretcher circuit triggers only on the transition of an off-chip generated clock input and determines the generated pulse width of the clock by means of an on-chip delay line. The circuit introduces only one stage of delay in the clock path.
    Type: Grant
    Filed: June 7, 1991
    Date of Patent: December 15, 1992
    Assignee: International Business Machines Corp.
    Inventor: Frank A. Montegari
  • Patent number: 5128561
    Abstract: A bipolar receiver which generates relatively large output voltage transitions. Current mirror regulated current steered by an ECL switch is mirrored to output transistors, allowing the output node to operate within one V.sub.be of the supply without saturation of the receiver transistors.
    Type: Grant
    Filed: June 18, 1991
    Date of Patent: July 7, 1992
    Assignee: International Business Machines Corporation
    Inventor: Frank A. Montegari
  • Patent number: 5109167
    Abstract: The present invention is directed to a decoder implemented with metal oxide semiconductor (MOS) field effect transistors (FETs) and a bipolar transistor in a collector-follower configuration. In one embodiment, NPN transistors perform decoding, FETs are used as pull-up devices and a PNP transistor in a collector-follower configuration is used to drive the output line. In a second embodiment, FETs perform decoding and are used as pull-up devices, and a PNP in a collector-follower configuration is used to drive the output line.
    Type: Grant
    Filed: December 28, 1990
    Date of Patent: April 28, 1992
    Assignee: International Business Machines Corp.
    Inventor: Frank A. Montegari
  • Patent number: 4831494
    Abstract: Disclosed is a multilayer capacitor consisting of a plurality of laminae with each of the laminae including a conductive plate portion and a non-conductive sheet portion. The conductive plate portion has at least one tab projecting to at least one edge of the conductive plate portion with the maximum number of tabs per conductive plate portion being limited to avoid excessive lateral congestion. The laminae are divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs.
    Type: Grant
    Filed: June 27, 1988
    Date of Patent: May 16, 1989
    Assignee: International Business Machines Corporation
    Inventors: Allen J. Arnold, Michael E. Bariether, Shin-Wu Chiang, Hormazdyar M. Dalal, Robert A. Miller, Frank A. Montegari, James M. Oberschmidt, David T. Shen
  • Patent number: 4570086
    Abstract: A high speed low power logic circuit, said logic circuit having at least first and second input terminals and an output terminal, said logic circuit accepting first and second binary inputs, respectively, at said first and second input terminals and providing a binary output at said output terminal, said binary output being a predetermined logical function of said first and second binary inputs, said logic circuit comprising: a first transistor, a second transistor and a first resistor serially connected between a first source of potential and a second source of potential, said first transistor being of first conductivity type and having an emitter, base and collector, said second transistor being of a second conductivity type opposite to said first conductivity type and having an emitter base and collector; a capacitor connected in parallel with said first resistor; a second resistor connected between said base of said second transistor and said second source of potential; first connections means passively c
    Type: Grant
    Filed: June 27, 1983
    Date of Patent: February 11, 1986
    Assignee: International Business Machines Corporation
    Inventors: James W. Bode, Frank A. Montegari
  • Patent number: 4531067
    Abstract: Logic circuit means for providing a binary output which is a predetermined logical function of a plurality of binary inputs, said logic circuit means including: at least first, second and third push-pull Darlington current sink (PPDCS) logic circuits, each said PPDCS logic circuit comprising: first, second and third transistors, each of said first, second and third transistors having an emitter, base and collector, said collector of said third transistor connected to a first source of potential and said emitter of said second transistor connected to a third source of potential; input circuit means, said input circuit means being adapted to receive n binary inputs, where n is a positive integer having a magnitude of two or greater, said input circuit means being connected to said collector of said first transistor and said base of said third transistor; a first resistor connected between said emitter of said first transistor and a second source of potential; a second resistor connected between said first sourc
    Type: Grant
    Filed: June 29, 1983
    Date of Patent: July 23, 1985
    Assignee: International Business Machines Corporation
    Inventors: Dennis C. Banker, Frank A. Montegari, John P. Norsworthy
  • Patent number: 4494017
    Abstract: The decode circuit utilizes NPN and PNP transistors and performs a complete decode function in only one logic level with the no need for a true/complement input of each binary input. A first embodiment of the decoder provides an UP level output when selected. A second embodiment of the decoder provides a DOWN level output when selected. The decode circuit may be used as an address decode circuit in a memory and also portion(s) of the decode circuit may be used independently as a binary logic circuit. Also disclosed is a complementary current switch logic circuit with dual phase outputs.
    Type: Grant
    Filed: March 29, 1982
    Date of Patent: January 15, 1985
    Assignee: International Business Machines Corporation
    Inventor: Frank A. Montegari
  • Patent number: 4129790
    Abstract: The disclosed logic circuit includes one transistor and a plurality of Schottky barrier diodes in each logic circuit "cell," a plurality of such cells being interconnected to perform desired logic functions. Cell interconnections are made by interconnecting metallurgy which can have a relatively high resistance with relatively long interconnecting paths between a sending circuit cell and a receiving circuit cell. The undesirable effects of this metallurgy resistance are overcome by driving the base of the receiving transistor through a base drive resistor in the sending cell.
    Type: Grant
    Filed: December 21, 1977
    Date of Patent: December 12, 1978
    Assignee: International Business Machines Corporation
    Inventors: Venkappa L. Gani, Frank A. Montegari