Patents by Inventor Frank Alexander Baiocchi

Frank Alexander Baiocchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10826487
    Abstract: One example relates to a circuit that includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die has a power field effect transistor (FET) and a pull-down FET coupled to the power FET. The second integrated circuit die has a pull-up FET coupled to the power FET.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: November 3, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Haian Lin, Frank Alexander Baiocchi, Scott Edward Ragona, Jonathan Almeria Noquil
  • Patent number: 10812064
    Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Alexander Baiocchi, Masahiko Higashi, Namiko Hagane
  • Publication number: 20200328275
    Abstract: In some examples, a semiconductor device, comprises a semiconductor substrate; an epitaxial layer having a top side disposed on the semiconductor substrate, wherein the epitaxial layer has a source implant region, a drain implant region, a first doped region, and a second doped region, wherein the first doped region is adjacent to the source implant region and the second doped region is adjacent to the drain implant region, wherein the top side has a sloped surface over the second doped region; a gate electrode supported by the top side; a source electrode in contact with the source implant region; and a drain electrode in contact with the drain implant region.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 15, 2020
    Inventors: Haian LIN, Frank Alexander BAIOCCHI, Seetharaman SRIDHAR
  • Publication number: 20200295748
    Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.
    Type: Application
    Filed: February 19, 2020
    Publication date: September 17, 2020
    Inventors: Haian Lin, Frank Alexander Baiocchi, Masahiko Higashi, Namiko Hagane
  • Patent number: 10581426
    Abstract: An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Alexander Baiocchi, Masahiko Higashi, Namiko Hagane
  • Publication number: 20190173464
    Abstract: One example relates to a circuit that includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die has a power field effect transistor (FET) and a pull-down FET coupled to the power FET. The second integrated circuit die has a pull-up FET coupled to the power FET.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Inventors: Haian Lin, Frank Alexander Baiocchi, Scott Edward Ragona, Jonathan Almeria Noquil