Patents by Inventor Frank Burmeister
Frank Burmeister has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230326765Abstract: A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.Type: ApplicationFiled: July 9, 2021Publication date: October 12, 2023Inventors: Xianming CHEN, Frank BURMEISTER, Lei FENG, Yujun ZHAO, Benxia HUANG, Jinxin YI, Jindong FENG, Yuan LI, Lina JIANG, Edward TENA, Wenshi WANG
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Publication number: 20230223325Abstract: The disclosure provides a semiconductor package substrate made from non-metallic material having a first top surface, a second bottom surface opposite from the first surface, and at least one side surface, the substrate includes at least two pads positioned on the first surface and suitable for receiving an electronic element, an encapsulant material layer covering the first surface, at least two terminals positioned on the second surface and electrically connected to the pads, and a portion of at least one of the two terminals is exposed at the at least one side surface and structured as a wettable flank.Type: ApplicationFiled: January 12, 2023Publication date: July 13, 2023Applicant: NEXPERIA B.V.Inventors: Yu Jun Zhao, Jin Xin Yi, Yuan Li, Frank Burmeister, Edward Tena
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Publication number: 20230154891Abstract: A substrate-based package semiconductor device is provided. The present disclosure further relates to a carrier including a plurality of non-singulated substrate-based package semiconductor devices and to a method of manufacturing the same. In embodiments in accordance with the present disclosure, the lowest insulating layer(s) has/have cavities arranged near and associated with one or more package terminals, and an inner wall of the cavities is covered with a conductive body that connects to the respective associated package terminal. Furthermore, the non-singulated substrate-based package semiconductor devices are separated by a separating region of the substrate, and the cavities are at least partially formed in the separating region.Type: ApplicationFiled: November 18, 2022Publication date: May 18, 2023Applicant: NEXPERIA B.V.Inventors: YuJun Zhao, JinXin Yi, Yuan Li, Frank Burmeister, Jennifer Schuett, Dicky Tirta Djaja, Qingyuan Tang
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Patent number: 11342357Abstract: A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.Type: GrantFiled: February 11, 2019Date of Patent: May 24, 2022Assignee: Nexperia B.V.Inventors: Hans-Martin Ritter, Frank Burmeister
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Patent number: 10546816Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.Type: GrantFiled: November 18, 2016Date of Patent: January 28, 2020Assignee: Nexperia B.V.Inventors: Hans-Martin Ritter, Joachim Utzig, Frank Burmeister, Godfried Henricus Josephus Notermans, Jochen Wynants, Rainer Mintzlaff
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Publication number: 20190252409Abstract: A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.Type: ApplicationFiled: February 11, 2019Publication date: August 15, 2019Applicant: NEXPERIA B.V.Inventors: Hans-Martin RITTER, Frank BURMEISTER
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Publication number: 20180166388Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.Type: ApplicationFiled: November 18, 2016Publication date: June 14, 2018Inventors: Hans-Martin Ritter, Joachim Utzig, Frank Burmeister, Godfried Henricus Josephus Notermans, Jochen Wynants, Rainer Mintzlaff
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Patent number: 9859184Abstract: A method of making a plurality of semiconductor devices comprising a chip scale packages. The method includes providing a semiconductor wafer having a major surface and a backside. The method also includes forming a plurality of contacts on the major surface. The method further includes forming a plurality of trenches in the major surface of the substrate. The method also includes forming a plurality of openings in the wafer between the backside and the trenches in the major surface. The method further includes depositing an encapsulant on the backside of the wafer. At least some of the encapsulant passes through the openings in the wafer to at least partially fill the trenches in the major surface. The method also includes singulating the wafer to produce a plurality of chip scale packages having a major surface including one or more contacts and side walls at least partially covered with said encapsulant.Type: GrantFiled: June 29, 2016Date of Patent: January 2, 2018Assignee: Nexperia B.V.Inventors: Hans-Martin Ritter, Frank Burmeister
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Patent number: 9806034Abstract: A method of protecting sidewalls a plurality of semiconductor devices is disclosed. The method includes fabricating the plurality of semiconductor devices on a semiconductor wafer, etching to form a trench grid network on the backside of the semiconductor wafer. The trench grid network demarcate physical boundaries of each of the plurality of semiconductor devices. The method also includes depositing a protective layer on the backside and etching to remove the protective layer from horizontal surfaces and to singulate each of the plurality of semiconductor devices from the semiconductor wafer.Type: GrantFiled: June 16, 2016Date of Patent: October 31, 2017Assignee: Nexperia B.V.Inventors: Hans-Juergen Funke, Tobias Sprogies, Rolf Brenner, Rüdiger Weber, Wolfgang Schnitt, Frank Burmeister
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Publication number: 20170256432Abstract: A method of packing a semiconductor device is disclosed. The method includes placing a wafer on a carrier such that a backside of the wafer is facing up and a front side is facing down and non-permanently affixed to the surface of the carrier, performing lithography to mark area to be etched on the backside of the wafer, etching the marked areas from the backside of the wafer thus forming trenches that mark boundaries of individual devices on the wafer, applying a protective coating on the backside of the wafer thus filling the trenches and entire backside of the wafer with a protective compound and cutting the individual devices from the wafer.Type: ApplicationFiled: March 3, 2016Publication date: September 7, 2017Inventors: Frank Burmeister, Chi Ho Leung, Zhigang Li, Yujun Zhao, Karen Kirchheimer, Hans-Martin Ritter
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Publication number: 20170170122Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.Type: ApplicationFiled: November 18, 2016Publication date: June 15, 2017Inventors: Hans-Martin Ritter, Joachim Utzig, Frank Burmeister, Godfried Henricus Josephus Notermans, Jochen Wynants, Rainer Mintzlaff
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Publication number: 20170033029Abstract: A method of making a plurality of semiconductor devices comprising a chip scale packages. The method includes providing a semiconductor wafer having a major surface and a backside. The method also includes forming a plurality of contacts on the major surface. The method further includes forming a plurality of trenches in the major surface of the substrate. The method also includes forming a plurality of openings in the wafer between the backside and the trenches in the major surface. The method further includes depositing an encapsulant on the backside of the wafer. At least some of the encapsulant passes through the openings in the wafer to at least partially fill the trenches in the major surface. The method also includes singulating the wafer to produce a plurality of chip scale packages having a major surface including one or more contacts and side walls at least partially covered with said encapsulant.Type: ApplicationFiled: June 29, 2016Publication date: February 2, 2017Inventors: Hans-Martin RITTER, Frank BURMEISTER
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Publication number: 20080223295Abstract: The invention is a method for producing a tool which can be used to create optically active surface structures in the sub-?m range, having a support surface onto which relief surface structures are applied over the support surface by means of material deposition. The invention is distinguished by the support surface being directly contacted with a mask in which openings with diameters in the sub-?m range are provided or can be provided, by the support surface including the mask being subjected to a coating process in which the coating material deposits through the openings of the mask onto the support surface, and the mask is removed from the support surface when a partial amount of an average end structure height of the surface structures is reached and the coating procedure is then continued without the mask using the same coating material or different coating materials.Type: ApplicationFiled: April 17, 2008Publication date: September 18, 2008Inventors: Frank Burmeister, Walter Doll, Gunter Kleer
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Patent number: 7390531Abstract: The invention is a method for producing a tool which can be used to create optically active surface structures in the sub-?m range, having a support surface onto which relief surface structures are applied over the support surface by means of material deposition. The invention is distinguished by the support surface being directly contacted with a mask in which openings with diameters in the sub-?m range are provided or can be provided, by the support surface including the mask being subjected to a coating process in which the coating material deposits through the openings of the mask onto the support surface, and the mask is removed from the support surface when a partial amount of an average end structure height of the surface structures is reached and the coating procedure is then continued without the mask using the same coating material or different coating materials.Type: GrantFiled: August 9, 2001Date of Patent: June 24, 2008Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.Inventors: Frank Burmeister, Walter Döll, Günter Kleer
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Publication number: 20040052946Abstract: The invention relates to a method for producing a tool, and a tool which can be used to create optically active surface structures in the sub-&mgr;m range. Said tool comprises a support surface to which surface structures are applied by depositing material, said surface structures being raised in relation to the support surface. The invention is characterised in that the support surface is in-directly bonded with a mask (2) in which openings (3) having diameters in the sub-&mgr;m range are provided or can be placed; the support surface and the mask are subjected to a coating process during which coating material is deposited onto the support surface via the openings (3) in the mask; the mask is removed from the support surface when a partial amount of the average height of the end structure pertaining to the surface structures is obtained; and the coating process is continued without a mask and with similar or different coating material.Type: ApplicationFiled: October 14, 2003Publication date: March 18, 2004Inventors: Frank Burmeister, Walter Doll, Gunter Kleer
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Patent number: 6391679Abstract: A method of processing a substantially wafer-shaped product in semiconductor technology is described, which product is designed for the formation of a number of electronic circuit bodies over at least a first of its main surfaces, which circuit bodies are to be mechanically separated substantially perpendicularly to the first main surface, and which product has a second main surface lying opposite the first main surface.Type: GrantFiled: November 4, 1999Date of Patent: May 21, 2002Assignee: U.S. Philips CorporationInventors: Joachim Anker, Olaf Dichte, Frank Burmeister