Patents by Inventor Frank Greer

Frank Greer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150179915
    Abstract: A dielectric for superconducting electronics (e.g., amorphous silicon, silicon oxide, or silicon nitride) is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. A fluorinant (gas or plasma) is injected into a process chamber, either continuously or as a series of pulses, while the dielectric is being formed by chemical vapor deposition on a substrate. To further reduce defects, the silicon may be deposited from a silicon precursor that includes multiple co-bonded silicon atoms, such as disilane or trisilane.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: INTERMOLECULAR, INC.
    Inventors: Frank Greer, Sergey Barabash, Dipankar Pramanik, Andrew Steinbach
  • Publication number: 20150140834
    Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Intermolecular Inc.
    Inventors: Kevin Kashefi, Frank Greer
  • Publication number: 20150132938
    Abstract: Methods are provided for the deposition of high-k gate dielectric materials which are doped with fluorine and/or nitrogen to improve the performance and reliability. The high-k dielectric materials may include at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium aluminum oxide, titanium oxide, titanium silicon oxide, or titanium aluminum oxide. The fluorine dopant is provided from a layer including titanium nitride or amorphous silicon, where the layer is doped with at least one of fluorine or nitrogen. The dopants diffuse into the high-k dielectric material during a subsequent anneal process.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: Intermolecular, Inc.
    Inventors: Khaled Ahmed, Frank Greer
  • Publication number: 20150118828
    Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Intermolecular Inc.
    Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
  • Patent number: 8975706
    Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Khaled Ahmed, Frank Greer
  • Publication number: 20150064361
    Abstract: Irradiation with ultraviolet (UV) light during atomic layer deposition (ALD) can be used to cleave unwanted bonds on the layer being formed (e.g., trapped precursor ligands or process-gas molecules). Alternatively, the UV irradiation can be used to excite the targeted bonds so they may be more easily cleaved by other means. The use of UV may enable the formation of low-defect-density films at lower deposition temperatures (e.g., <250 C), or reduce the need for a high-temperature post-deposition anneal, improving the quality of devices formed on heat-sensitive materials such as germanium.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: Intermolecular Inc.
    Inventors: Frank Greer, Amol Joshi, Kevin Kashefi
  • Publication number: 20150041912
    Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
    Type: Application
    Filed: December 19, 2013
    Publication date: February 12, 2015
    Applicant: Intermolecular, Inc.
    Inventors: Khaled Ahmed, Frank Greer
  • Publication number: 20150035085
    Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.
    Type: Application
    Filed: December 17, 2013
    Publication date: February 5, 2015
    Applicant: Intermolecular Inc.
    Inventors: Khaled Ahmed, Frank Greer
  • Patent number: 8906791
    Abstract: Methods, apparatus, and systems for depositing materials with gaseous precursors are provided. In certain implementations, the methods involve providing a wafer substrate to a chamber of an apparatus. The apparatus includes a showerhead to deliver a gas to the chamber, a volume, and an isolation valve between the volume and the showerhead. A gas is delivered the volume when the isolation valve is closed, pressurizing the volume. The isolation valve is opened to allow the gas to flow to the showerhead when the gas is being delivered to the volume. A material is formed on the wafer substrate using the gas. In some implementations, releasing the pressurized gas from the volume reduces the duration of time to develop a spatially uniform gas flow across the showerhead.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 9, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Kie-Jin Park, Karl Leeser, Frank Greer, David Cohen
  • Patent number: 8906709
    Abstract: Provided are methods of high productivity combinatorial (HPC) inspection of semiconductor substrates. A substrate includes two layers of dissimilar materials interfacing each other, such as a stack of a silicon bottom layer and an indium gallium arsenide top layer. The dissimilar materials have one or more of thermal, structural, and lattice mismatches. As a part of the inspection, the top layer is etched in a combinatorial manner. Specifically, the top layer is divided into multiple different site-isolated regions. One such region may be etched using different process conditions from another region. Specifically, etching temperature, etching duration and/or etchant composition may vary among the site-isolated regions. After combinatorial etching, each region is inspected to determine its etch-pit density (EPD) value. These values may be then analyzed to determine an overall EPD value for the substrate, which may involve discarding EPD values for over-etched and under-etched regions.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Khaled Ahmed, Frank Greer, George Mirth, Zhi-Wen Sun
  • Patent number: 8901677
    Abstract: A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeO2 promotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: December 2, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Frank Greer, Edwin Adhiprakasha, Chi-I Lang, Ratsamee Limdulpaiboon, Sandip Niyogi, Kurt Pang, J. Watanabe
  • Publication number: 20140335823
    Abstract: A mobile electronic communications device includes a housing, a memory, a data entry mechanism, a display for visual data, at least one wireless transceiver configured to transmit and receive electromagnetic signals conforming to a plurality of wireless signaling protocols, and a controller. The controller is communicatively connected to the memory, data entry mechanism, and display; and is configured to send and receive data using the at least one wireless transceiver.
    Type: Application
    Filed: December 29, 2010
    Publication date: November 13, 2014
    Applicant: ZIPIT WIRELESS, INC.
    Inventors: Rafael Heredia, Michael Crowe, Frank Greer, Joseph Ellis, Jordan Upham, William Matson
  • Publication number: 20140252565
    Abstract: A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeO2 promotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Frank Greer, Edwin Adhiprakasha, Chi-I Lang, Ratsamee Limdulpaiboon, Sandip Niyogi, Kurt Pang, J. Watanabe
  • Patent number: 8828852
    Abstract: Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3+NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: September 9, 2014
    Assignee: California Institute of Technology
    Inventors: Michael E. Hoenk, Shoulch Nikzad, Todd J. Jones, Frank Greer, Alexander G. Carver
  • Publication number: 20140167198
    Abstract: A back-illuminated silicon photodetector has a layer of Al2O3 deposited on a region of a silicon oxide surface that is left uncovered, while deposition is inhibited in another region by a contact shadow mask. The Al2O3 layer is an antireflection coating. In addition, the Al2O3 layer can also provide a chemically resistant separation layer between the silicon oxide surface and additional antireflection coating layers. In one embodiment, the silicon photodetector has a delta-doped layer near (within a few nanometers of) the silicon oxide surface. The Al2O3 layer is expected to provide similar antireflection properties and chemical protection for doped layers fabricated using other methods, such as MBE, ion implantation and CVD deposition.
    Type: Application
    Filed: February 21, 2014
    Publication date: June 19, 2014
    Inventors: Michael E. Hoenk, Frank Greer, Shouleh Nikzad
  • Patent number: 8697474
    Abstract: Embodiments of the invention provide for fabricating a filter, for electromagnetic radiation, in at least three ways, including (1) fabricating integrated thin film filters directly on a detector; (2) fabricating a free standing thin film filter that may be used with a detector; and (3) treating an existing filter to improve the filter's properties.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: April 15, 2014
    Assignee: California Institute of Technology
    Inventors: Frank Greer, Shouleh Nikzad
  • Patent number: 8680637
    Abstract: A back-illuminated silicon photodetector has a layer of Al2O3 deposited on a silicon oxide surface that receives electromagnetic radiation to be detected. The Al2O3 layer has an antireflection coating deposited thereon. The Al2O3 layer provides a chemically resistant separation layer between the silicon oxide surface and the antireflection coating. The Al2O3 layer is thin enough that it is optically innocuous. Under deep ultraviolet radiation, the silicon oxide layer and the antireflection coating do not interact chemically. In one embodiment, the silicon photodetector has a delta-doped layer near (within a few nanometers of) the silicon oxide surface. The Al2O3 layer is expected to provide similar protection for doped layers fabricated using other methods, such as MBE, ion implantation and CVD deposition.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 25, 2014
    Assignee: California Institute of Technology
    Inventors: Michael E. Hoenk, Frank Greer, Shouleh Nikzad
  • Publication number: 20130157465
    Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
    Type: Application
    Filed: February 5, 2013
    Publication date: June 20, 2013
    Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
  • Patent number: 8435895
    Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: May 7, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
  • Publication number: 20120168891
    Abstract: High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches.
    Type: Application
    Filed: October 25, 2011
    Publication date: July 5, 2012
    Applicant: California Institute of Technology
    Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Michael E. Hoenk