Patents by Inventor Frank J. Juskey

Frank J. Juskey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9269887
    Abstract: Embodiments include but are not limited to apparatuses and systems including microelectronic devices including a package substrate, a plurality of electronic components disposed on and electrically coupled with the package substrate at one or more sides of the package substrate, one or more hollow cavity sheet molds surrounding the plurality of electronic components and coupled with one or more sides of the package substrate, and a plurality of through-mold vias to couple the package substrate with an external surface of at least one of the one or more hollow cavity sheet molds. The microelectronic device may be a chip-scale package or module. Methods and systems for making the same also are described.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: February 23, 2016
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Frank J. Juskey, Robert C. Hartmann, Thomas S. Morris, Howard T. Glascock, Jose F. Ordonez
  • Publication number: 20140106511
    Abstract: Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 17, 2014
    Applicant: TriQuint Semiconductor, Inc.
    Inventors: Frank J. Juskey, Robert C. Hartmann, Paul D. Bantz
  • Patent number: 8680683
    Abstract: A wafer level package includes an epoxy layer formed on an adhesive covered substrate during manufacturing for securing electrical components in place prior to being embedded in a molded material. An electrically conductive block is fixed in the epoxy layer. Vias are formed for accessing face up component contacts using a metalized layer on the surface of the molded material. After stripping the adhesive and substrate, the epoxy layer is penetrated to expose electrical contacts for face down components. An electrical connection is made between the face up and face down components using the block. Optionally, a dielectric layer covers the molded material and a second metalized layer placed on the dielectric layer to carry another electrical component embedded in a second dielectric layer covering the first dielectric layer. Thus a stacked component arrangement including multiple die and passive components is effectively fabricated into the wafer level package.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: March 25, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Frank J. Juskey, Robert C. Hartmann
  • Publication number: 20130234344
    Abstract: Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: TRIQUINT SEMICONDUCTOR, INC.
    Inventors: Frank J. Juskey, Robert C. Hartmann, Paul D. Bantz
  • Patent number: 8487435
    Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: July 16, 2013
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Frank J. Juskey, Paul Bantz, Otto Berger
  • Publication number: 20120080768
    Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 5, 2012
    Applicant: TRIQUINT SEMICONDUCTOR, INC.
    Inventors: Frank J. Juskey, Paul Bantz, Otto Berger
  • Patent number: 7489021
    Abstract: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected to the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: February 10, 2009
    Assignee: Advanced Interconnect Technologies Limited
    Inventors: Frank J. Juskey, Daniel K. Lau, Lawrence R. Thompson
  • Publication number: 20080036034
    Abstract: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).
    Type: Application
    Filed: February 17, 2004
    Publication date: February 14, 2008
    Inventors: Frank J. Juskey, Daniel K. Lau, Lawrence R. Thompson
  • Patent number: 7247933
    Abstract: A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substanial exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) form a cavity (102).
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: July 24, 2007
    Assignee: Advanced Interconnect Technologies Limited
    Inventors: Frank J. Juskey, Daniel K. Lau
  • Patent number: 6507102
    Abstract: A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: January 14, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Frank J. Juskey, John R. McMillan, Ronald P. Huemoeller
  • Publication number: 20020043402
    Abstract: A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press.
    Type: Application
    Filed: December 5, 2001
    Publication date: April 18, 2002
    Inventors: Frank J. Juskey, John R. McMillan, Ronald P. Huemoeller
  • Patent number: 6340846
    Abstract: This invention provides a method for making a semiconductor package with stacked dies that substantially reduces risk of fracturing of the dies and prevents breakage of the wire bonds caused by wire sweep. One embodiment of the method includes the provision of a substrate and a pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed out to the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured and the second die is wire bonded to the substrate. A bead of an adhesive is dispensed around the periphery of the dies such that it covers the wire bonds and bonding pads on the second die.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: January 22, 2002
    Assignee: Amkor Technology, Inc.
    Inventors: Anthony J. LoBianco, Frank J. Juskey, Stephen G. Shermer, Vincent DiCaprio, Thomas P. Glenn
  • Patent number: 6337228
    Abstract: A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: January 8, 2002
    Assignee: Amkor Technology, Inc.
    Inventors: Frank J. Juskey, John R. McMillan, Ronald P. Huemoeller
  • Patent number: 5800723
    Abstract: A process (200) for fabricating a flex circuit (708, 806, 812, 818 or 824) using a fabrication process without the use of a photomask includes the steps of generating (412) an electronic image (702 or 802) of circuit traces (704 or 804) representing at least a single-sided flex circuit, and selectively thermal transferring (506 or 606) a resin to either a conductively clad or non-conductive flexible substrate (304) under the control of the electronic image (702 or 802) to form either an etch resist or a conductor which defines the circuit traces (704 or 804). The conductively clad flexible substrate (304) is etched to form the circuit traces (704 or 804) of the flex circuit defined by the etch resist, after which the etch resist is removed.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: September 1, 1998
    Assignee: Motorola, Inc.
    Inventors: Frank J. Juskey, Douglas W. Hendricks, Sally A. Stallings
  • Patent number: 5542171
    Abstract: A method of making a transfer molded chip carrier. A semiconductor device (10) is first electrically and mechanically attached to a substrate (12). The substrate (12) is then treated by sputter etching so that it will provide good adhesion between the substrate and a molding compound (18) that is subsequently molded to the substrate (25). Portions of the treated substrate are then selectively contaminated in order to reduce the adhesion between these selected portions of the substrate and the molding compound. The molding compound is then formed around the semiconductor device so as to encapsulate it and also part of the surface of the substrate. Portions (20) of the transfer molded material that were molded over the selectively contaminated portions of the substrate (12) are then removed by breaking away.
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: August 6, 1996
    Assignee: Motorola, Inc.
    Inventors: Frank J. Juskey, Anthony B. Suppelsa, Fadia Nounou
  • Patent number: 5535101
    Abstract: A semiconductor device package comprises an integrated circuit chip (10), a substrate (16), an encapsulant (30), and an organic coupling agent or underfill material (12) disposed between the integrated circuit chip and the first side of the substrate. The chip has a plurality of interconnection pads (14) disposed on an active surface of the chip at some minimum spacing "X." Each of the interconnect pads also has electrically conducting bumps (26) on them. The substrate has a circuit pattern (20) on a first side and an array of solder pads (23) spaced a certain distance apart on an opposite side of the substrate. The distance between these pads is greater than the minimum distance (X) between the interconnect pads on the IC. The circuit pattern is electrically connected to the array of solder pads by plated through holes (22). The length and width of the circuit carrying substrate is substantially greater than the length and width of the integrated circuit chip.
    Type: Grant
    Filed: November 3, 1992
    Date of Patent: July 9, 1996
    Assignee: Motorola, Inc.
    Inventors: Barry M. Miles, Frank J. Juskey, Kingshuk Banerji
  • Patent number: 5463190
    Abstract: A conductive adhesive (120) for electrically and mechanically bonding circuit terminals (105) includes a polymer (121) having a predetermined curing temperature range, a first conductive particulate material (125) suspendable in the polymer (121) for providing substantially uniform conductivity throughout the conductive adhesive (120), and a second conductive particulate material (130) suspendable in the polymer (121) for metallurgically bonding together particles of the first particulate material (125). The first conductive particulate material (125) provides substantially uniform conductivity throughout the conductive adhesive (120) and includes metallic particles having a melting point above the curing temperature of the polymer. The second conductive particulate material (130) welds together particles of the first particulate material (125) and includes metallic particles having a melting point within the curing temperature range of the polymer (121).
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: October 31, 1995
    Assignee: Motorola, Inc.
    Inventors: Robert T. Carson, Arnold W. Hogrefe, Frank J. Juskey, Jr.
  • Patent number: 5438224
    Abstract: An integrated circuit package includes a stacked integrated circuit chip arrangement (140) placed on a circuit substrate. The stacked IC chip arrangement includes a first IC chip (110) and a second IC chip (120), each having an array of terminals (116, 126) and being positioned in a face-to-face manner. An interposed substrate (130) is positioned between the first IC chip (110) and the second IC chip (120) such that circuitry disposed on the interposed substrate (130) provides electrical connection among the arrays of terminals of the first IC chip (110) and the second IC chip (120) and external circuitry.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: August 1, 1995
    Assignee: Motorola, Inc.
    Inventors: Marc V. Papageorge, Bruce J. Freyman, Frank J. Juskey, John R. Thome
  • Patent number: 5438216
    Abstract: A multichip circuit package is formed for use with an EPROM chip. The active circuitry on the EPROM die surface is revealed. An EPROM die (14) is mounted on an insulating substrate (10). The active circuitry (15) on the die is connected to a conductive circuit pattern (13) on the substrate by wire bonds (16) between the die and the conductive circuit pattern. A second integrated circuit die (20) is also mounted on the substrate and electrically connected to the conductive circuit pattern by wire bonds. A plastic material (50) is then molded to encapsulate the perimeter (18) of the EPROM and the associated thin wires, the entire second integrated circuit die and it's associated thin wires, at least a portion of the conductive circuit pattern, and portions of the insulating substrate. The plastic material is formed so as to expose the active circuitry on the face of the EPROM.
    Type: Grant
    Filed: August 31, 1992
    Date of Patent: August 1, 1995
    Assignee: Motorola, Inc.
    Inventors: Frank J. Juskey, Anthony B. Suppelsa, Dale W. Dorinski
  • Patent number: 5371404
    Abstract: A semiconductor device package comprises a substrate (10), a flip-chip (16), an underfill adhesive (25), and a thermally and electrically conductive plastic material (20). A leadless circuit carrying substrate has a metallization pattern (13) on a first side (15), one portion of the metallization pattern being a circuit ground (17). The second side has an array of surface mount solder pads (24) electrically connected to the metallization pattern by means of at least one conductive via (26) through the substrate. A semiconductor device (16) is flip-chip mounted to the metallization pattern by means of metal bumps (22). An underfill adhesive (25) fills the gap between the semiconductor device and the substrate. A thermally and electrically conductive plastic material (20) containing metal particles is transfer molded to encapsulate the semiconductor device, the underfill adhesive, and a portion of the first side of the leadless circuit carrying substrate, forming a cover.
    Type: Grant
    Filed: February 4, 1993
    Date of Patent: December 6, 1994
    Assignee: Motorola, Inc.
    Inventors: Frank J. Juskey, Anthony B. Suppelsa