Patents by Inventor Frank Randolph Bryant
Frank Randolph Bryant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7704841Abstract: A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.Type: GrantFiled: October 31, 2008Date of Patent: April 27, 2010Assignee: STMicroelectronics, Inc.Inventor: Frank Randolph Bryant
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Publication number: 20090124055Abstract: A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.Type: ApplicationFiled: October 31, 2008Publication date: May 14, 2009Inventor: Frank Randolph Bryant
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Patent number: 7488611Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.Type: GrantFiled: December 6, 2005Date of Patent: February 10, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
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Patent number: 7459758Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.Type: GrantFiled: May 16, 2001Date of Patent: December 2, 2008Assignee: STMicroelectronics, Inc.Inventor: Frank Randolph Bryant
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Patent number: 7004558Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.Type: GrantFiled: October 25, 2002Date of Patent: February 28, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
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Patent number: 6780718Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.Type: GrantFiled: November 30, 1993Date of Patent: August 24, 2004Assignee: STMicroelectronics, Inc.Inventor: Frank Randolph Bryant
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Patent number: 6740536Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.Type: GrantFiled: October 26, 2001Date of Patent: May 25, 2004Assignee: Hewlett-Packard Develpment Corporation, L.P.Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
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Publication number: 20030207477Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.Type: ApplicationFiled: October 25, 2002Publication date: November 6, 2003Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
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Publication number: 20030080362Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.Type: ApplicationFiled: October 26, 2001Publication date: May 1, 2003Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
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Patent number: 6498079Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.Type: GrantFiled: July 27, 2000Date of Patent: December 24, 2002Assignee: STMicroelectronics, Inc.Inventors: Frank Randolph Bryant, Kenneth Wayne Smiley
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Patent number: 6472246Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.Type: GrantFiled: December 28, 1999Date of Patent: October 29, 2002Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Frank Randolph Bryant
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Publication number: 20020031870Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.Type: ApplicationFiled: May 16, 2001Publication date: March 14, 2002Inventor: Frank Randolph Bryant
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Patent number: 6303452Abstract: A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. The oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.Type: GrantFiled: April 24, 1995Date of Patent: October 16, 2001Assignee: STMicroelectronics, Inc.Inventors: Fusen E. Chen, Frank Randolph Bryant, Girish Anant Dixit
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Patent number: 6271063Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.Type: GrantFiled: June 14, 2000Date of Patent: August 7, 2001Assignee: STMicroelectronics, Inc.Inventors: Tsiu Chiu Chan, Frank Randolph Bryant
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Patent number: 6188056Abstract: Disclosed is a CMOS image sensor that includes pixels employing a radiation-sensitive resistive element in which the resistance of the element changes in response to the quantity of radiation striking it. The resistive elements are made from an appropriately doped polycrystalline semiconductor material such as polysilicon. The pixels are provided on a semiconductor device in which the photosensitive resistive elements are provided on a first layer and the pixel associated transistors are provided on a second layer. The fill factor may be approach 100 percent for such pixels.Type: GrantFiled: June 24, 1998Date of Patent: February 13, 2001Assignee: STMicroelectronics, Inc.Inventors: Alexander Kalnitsky, Frank Randolph Bryant, Marco Sabatini
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Patent number: 6188112Abstract: A high impedance load for an integrated circuit device provides an undoped, or lightly doped, layer of epitaxial silicon. The epitaxial silicon layer is formed over a conductive region in a substrate, such as a source/drain region. A highly conductive contact, such as a refractory metal silicide interconnect layer, is formed on top of the epitaxial silicon layer. Preferably, the epitaxial silicon layer is formed using solid phase epitaxy, from excess silicon in the silicide layer, by annealing the device after the silicide layer has been deposited.Type: GrantFiled: February 3, 1995Date of Patent: February 13, 2001Assignee: STMicroelectronics, Inc.Inventor: Frank Randolph Bryant
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Patent number: 6140684Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.Type: GrantFiled: June 24, 1997Date of Patent: October 31, 2000Assignee: STMicroelectronic, Inc.Inventors: Tsiu Chiu Chan, Frank Randolph Bryant
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Patent number: 6091082Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.Type: GrantFiled: February 17, 1998Date of Patent: July 18, 2000Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Frank Randolph Bryant
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Patent number: 6034410Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.Type: GrantFiled: February 11, 1999Date of Patent: March 7, 2000Assignee: STMicroelectronics, Inc.Inventors: Tsiu Chiu Chan, Frank Randolph Bryant
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Patent number: RE40579Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.Type: GrantFiled: October 20, 2000Date of Patent: November 25, 2008Assignee: STMicroelectronics, Inc.Inventors: Frank Randolph Bryant, Tsiu Chiu Chan