Patents by Inventor Frank S. Smith

Frank S. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200122142
    Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Frank B. Myers, III, Clay D. Reber, Taber H. Smith, Faisal S. Maniar
  • Patent number: 10609961
    Abstract: The present disclosure relates to systems, apparatuses, and methods for assembling cartridges for aerosol delivery devices. The cartridges may be assembled by transporting carriages between various substations at which parts are added to a base. In another assembly method, the base may be moved between a plurality of robots which direct the base downwardly into contact with components to couple the components therewith. An inspection system may inspect the cartridges at various stages of completion.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 7, 2020
    Assignee: RAI STRATEGIC HOLDINGS, INC.
    Inventors: Frederic Philippe Ampolini, Timothy Brian Nestor, Jack Gray Flinchum, Jr., Wayne Douglas Brown, Nicholas Harrison Watson, Charles Jacob Novak, III, Paul Andrew Brinkley, James Robert Covino, John DePiano, Edward Louis Dickinson, Eugene R. Harris, Kevin Edward Keough, David Jay Smith, John Hook, Michael LaCourse, Robert Metcalf, Steven Hart, David Pelletier, Marc Bourque, Nathaniel Cambray, John William Wolber, James William McClellan, Steven R. Mongillo, Frank S. Silveira, Michael Laine, Quentin Paul Guenther, Jr.
  • Patent number: 10588352
    Abstract: The present disclosure relates to systems, apparatuses, and methods for assembling cartridges for aerosol delivery devices. The cartridges may be assembled by transporting carriages between various substations at which parts are added to a base. In another assembly method, the base may be moved between a plurality of robots which direct the base downwardly into contact with components to couple the components therewith. An inspection system may inspect the cartridges at various stages of completion.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 17, 2020
    Assignee: RAI STRATEGIC HOLDINGS, INC.
    Inventors: Frederic Philippe Ampolini, Timothy Brian Nestor, Jack Gray Flinchum, Jr., Wayne Douglas Brown, Nicholas Harrison Watson, Charles Jacob Novak, III, Paul Andrew Brinkley, James Robert Covino, John DePiano, Edward Louis Dickinson, Eugene R. Harris, Kevin Edward Keough, David Jay Smith, John Hook, Michael LaCourse, Robert Metcalf, Steven Hart, David Pelletier, Marc Bourque, Nathaniel Cambray, John William Wolber, James William McClellan, Steven R. Mongillo, Frank S. Silveira, Michael Laine, Quentin Paul Guenther, Jr.
  • Patent number: 10549275
    Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 4, 2020
    Assignee: Lucira Health, Inc.
    Inventors: Frank B. Myers, III, Clay D. Reber, Taber H. Smith, Faisal S. Maniar
  • Patent number: 10493923
    Abstract: A vehicle seat having a vehicle seat hook assembly for hanging an associated object on the vehicle seat includes a seat back having a front side, a rear side, and an upper distal portion and a headrest moveably secured to the upper distal portion for movement between a headrest retracted position and a headrest extended position. A seat hook is disposed on the seat back and is moveable between a seat hook retracted or collapsed position and a seat hook extended or sprung position. Movement of the headrest from the headrest retracted position to the headrest extended position causes movement of the seat hook from the seat hook retracted position to the seat hook extended position and movement of the headrest from the headrest extended position to the headrest retracted position causes movement of the seat hook from the seat hook extended position to the seat hook retracted position.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Honda Motor Co., Ltd.
    Inventors: Frank D. Moburg, Yuri A. Starik, Joan R. Smith, Andrew E. Barrow, Jeffrey H. Scheurer, II, Adam M. Parker, Andrea S. Martin, Samuel D. Goodrow
  • Patent number: 10470497
    Abstract: The present disclosure relates to systems, apparatuses, and methods for assembling cartridges for aerosol delivery devices. The cartridges may be assembled by transporting carriages between various substations at which parts are added to a base. In another assembly method, the base may be moved between a plurality of robots which direct the base downwardly into contact with components to couple the components therewith. An inspection system may inspect the cartridges at various stages of completion.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 12, 2019
    Assignee: RAI Strategic Holdings, Inc.
    Inventors: Frederic Philippe Ampolini, Timothy Brian Nestor, Jack Gray Flinchum, Jr., Wayne Douglas Brown, Nicholas Harrison Watson, Charles Jacob Novak, III, Paul Andrew Brinkley, James Robert Covino, John DePiano, Edward Louis Dickinson, Eugene R. Harris, Kevin Edward Keough, David Jay Smith, John Hook, Michael LaCourse, Robert Metcalf, Steven Hart, David Pelletier, Marc Bourque, Nathaniel Cambray, John William Wolber, James William McClellan, Steven R. Mongillo, Frank S. Silveira, Michael Laine, Quentin Paul Guenther, Jr.
  • Publication number: 20190262201
    Abstract: A patient support apparatus may include a support surface configured to conduct air along a top face of the support surface so that heat and moisture from a patient lying on the support surface are drawn away from the top face of the support surface. An opening may be formed in a side of the support surface. A cavity may extend from the opening into the support surface. An inlet port may be positioned within the cavity and fluidly coupled to the top face. A blower assembly may be configured to position within the cavity. The blower assembly may have an outlet port that couples to the inlet port when the blower assembly is positioned within the cavity. The blower assembly may conduct air through the inlet port to the top face of the support surface.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 29, 2019
    Inventors: Darrell L. Borgman, Douglas E. Borgman, Arpit Shah, Wui Hsien Wong, Keith Moores, Jason M. Gilreath, Michael R. Montini, Charles A. Lachenbruch, Eric R. Meyer, Frank E. Sauser, Catherine M. Wagner, Rachel L. Williamson, Brandon P. Fisk, Jason B. Grace, Brian Guthrie, Nicole Johannigman, Gregory J. Shannon, David C. Newkirk, Michael Churilla, Jnanesha Ramegowda, Taylor Franklin, Kathryn R. Smith, John G. Byers, Frederick K. Schultz, Andrew R. Wager, Sridhar Karimpuzha Seshadri, Gary R. Gibbons, Scott M. Corbin, John Goewert, Thomas L. Simpson, Faron L. Blessing, James D. Voll, Kin Meng Choi, Stephen S. Amrhein, Herve Gautier, Jean-Francois Lellig, Philippe Kaikenger, Matthieu Guetta
  • Publication number: 20190264746
    Abstract: A composite material having an alloy matrix including titanium, aluminum, niobium, manganese, boron, and carbon is disclosed. The composite material includes, by atomic percentage, 40.0% to 50.0% Al, 1.0% to 8.0% Nb, 0.5% to 2.0% Mn, 0.1% to 2.0% B, and 0.01% to 0.2% C. The composite material is doped with a solid lubricant such as MoS2, ZnO, CuO, hexagonal boron nitride (hBN), WS2, AgTaO3, CuTaO3, CuTa2O6, or combinations thereof. Components composed of the composite material exhibit increased ductility at room temperature and reduced fracture tendency, resulting in improved durability.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Applicant: Roller Bearing Company of America, Inc.
    Inventors: Frank C. Adams, Mark Heuberger, Charles E. Smith, Patrick S. Boyan, Ernest K. Robinson
  • Patent number: 6378061
    Abstract: An instruction decoder that issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents (106) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes them to the machine bus (110) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: April 23, 2002
    Assignee: Intel Corporation
    Inventors: Adrian Carbine, Glenn J. Hinton, Frank S. Smith
  • Patent number: 5459845
    Abstract: A microprocessor comprised of Instruction Fetch Unit (10), Instruction Decoder (12), Pipeline Sequencer (14), Register File (16), Multiply/Divider-Unit, Execution Unit, and REG coprocessors block (18) and instruction cache, Address Generation Unit, local register cache, and MEM coprocessors block (20). The Instruction Cache provides the Instruction fetch unit (10) with instructions every cycle. The instruction sequencer (IS) includes the Fetch Unit (IFU-10), the Instruction Decoder (ID-12) and the Pipeline Sequencer (PS-14). The instruction sequencer can decode and issue up to three instructions per clock. The pipe sequencer (14) employs a write back path to store snap shots of the state of the machine in pipe stages 1 and 2.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: October 17, 1995
    Assignee: Intel Corporation
    Inventors: Truong Nguyen, Frank S. Smith
  • Patent number: 5454089
    Abstract: Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the selected word. A full adder (40) adds this displacement to the instruction pointer. The result is used as the branch address. The timing is such that a 1 clock lookahead is sufficient to hide this calculation from program execution. The branch register address is determined by the process ID and the macro mode state bit. The branch by pass mechanism causes the branch address to be driven from the calculation instead of a branch register. If a branch fail or scoreboard hit occurs, a write cancellation is generated to stop the current address calculation from being stored in a branch register. If a branch fail or scoreboard hit does not occur, then the current address calculation is stored in a branch register. If a branch bypass occurs, then the branch address is driven from the calculation.
    Type: Grant
    Filed: October 26, 1993
    Date of Patent: September 26, 1995
    Assignee: Intel Corporation
    Inventors: Truong Nguyen, Frank S. Smith
  • Patent number: 5428811
    Abstract: An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functional units capable of independently executing second microinstructions that take a single clock cycle to complete execution. The first and second microinstructions are issued by an instruction decoder. A microintruction bus (112) is connected to the instruction decoder, the register file, and to each of the first and second functional units. A REG interface and a destination bus (110) are also connected to the register file (6). A Scbok line (102) is connected between the instruction unit, the register file and to each one of the first and second functional units. The instruction decoder includes means for asserting the Scbok line to signal that a current microinstruction on the microintruction bus (112) is valid.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: June 27, 1995
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Frank S. Smith, Randy Steck
  • Patent number: 5313605
    Abstract: A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: May 17, 1994
    Assignee: Intel Corporation
    Inventors: Scott Huck, Sunil Shenoy, Frank S. Smith
  • Patent number: 5222244
    Abstract: An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: June 22, 1993
    Assignee: Intel Corporation
    Inventors: Adrian Carbine, Frank S. Smith
  • Patent number: 5185872
    Abstract: A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory interface unit. Each unit connected to the scbok line can pull the line to indicate that it is busy. Each unit connected to the mem scbok line can pull the line to indicate that it is busy. The scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a register file operation. The mem scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a memory operation. Registers are checked concurrently with the issuing of an instruction.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: February 9, 1993
    Assignee: Intel Corporation
    Inventors: James M. Arnold, Glenn J. Hinton, Frank S. Smith
  • Patent number: 5023844
    Abstract: A random access memory cell in a register file having multiple independent read ports and multiple independent write ports that support parallel instruction execution. The RAM cell consumes low power and conforms to a tight layout pitch to meet the needs of the random access memory. A single column line is used, with the storage latch device (M 11, M 12) increased in size to provide for the noise margin loss with reference to the prior art two-column design. A single n-device (M 1) is attached to the opposite side of the cell latch (M 11, M 12) to clear the cell prior to writing zeros into the cell. The registers that are to be written are first cleared in the PH2 of the first clock cycle, with the data written in PH1 of the second clock cycle which writes the ones. The zero bits are also written at this time, but they find a cell that already is in the zero state, having been cleared in PH2 of the first clock cycle.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: June 11, 1991
    Assignee: Intel Corporation
    Inventors: James M. Arnold, Glenn J. Hinton, Frank S. Smith
  • Patent number: H1291
    Abstract: A microprocessor having a memory coprocessor (10) connected to a MEM interface (16) and a register coprocessor (12) connected to a REG interface (14). The REG interface (14) and MEM interface (16) are connected to independent read and write ports of a register file (6). An Instruction Sequencer (7) also connected to an independent write port of the register file, to the REG interface and to the MEM interface. An Instruction Cache (9) supplies the instruction sequencer with at least two instruction words per clock (7). Single-cycle coprocessors (4) are connected to the REG interface (14) and a multiple-cycle coprocessors (2) are connected to the REG interface (14). An Address Generation Unit (3) is connected to the MEM interface (16) for executing load-effective-address instructions and address computations for loads and stores to thereby perform effective address calculations in parallel with instruction execution by the single-cycle coprocessor.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: February 1, 1994
    Inventors: Glenn J. Hinton, Frank S. Smith