Abstract: A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics. First multiplexers are respectively coupled between adjacent sequential channels of a plurality of sequential channels under test. Each of the first multiplexers selectively receives a first data input in a first scan mode with the sequential channels configured in a common scan path and a second data input in a second scan mode with each the sequential channels configured in a separate scan path responsive to a first control signal. A first multiple input signature register (MISR) including multiple MISR inputs is coupled to a respective one of the plurality of sequential channels under test. A blocker function is configured for blocking all MISR inputs except for a single MISR input receiving the test data output of the last sequential channel responsive to a recirculate control signal. A second MISR shadow register is coupled to the first multiple input signature register.

Abstract: A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics of intermittent failures. A respective one of a plurality of first multiplexers is coupled between adjacent sequential channels of a plurality of sequential channels under test. Each of the first multiplexers selectively receives a first data input in a first scan mode with the sequential channels configured in a common scan path and a second data input in a second scan mode with each the sequential channels configured in a separate scan path responsive to a first control signal. A second multiplexer, coupled between a test data output of a last sequential channel and the first data input of a first sequential channel; selectively receives the test data output of the last sequential channel and an external test data input responsive to a recirculated control signal.

Abstract: According to the present invention, methods for testing interconnections on an electronic assembly in accordance with the disclosed embodiments eliminate some or all signal line contention during boundary scan testing. Each of these methods assumes that a first sequence of test patterns for testing the interconnects has been generated. A method in accordance with the first embodiment determines a safe pattern, and inserts the safe pattern between every two patterns in the first sequence of test patterns to generate a second sequence of test patterns. A method in accordance with the second embodiment analyzes the first sequence of test patterns, determines when a transition between two test patterns may cause possible signal contention, and inserts a safe test pattern between the two to generate a second sequence of test patterns. When a transition between two test patterns may potentially cause contention, the transition is said to be unsafe.

Abstract: Methods for testing interconnections on an electronic assembly include the steps of dynamically generating an interconnect topology model from one system, generating test patterns to test the interconnections, applying the test patterns to the boundary scan cells of the system under test to test the interconnections, and determining whether the interconnections match the interconnect topology model. The invention thus dynamically generates an interconnect topology model from a known working system, rather than deriving the interconnect topology model from design data that describes all the interconnections on an electronic assembly.

Abstract: A boundary scan register allows for simplified testing of interconnections between integrated circuits. The interconnections between integrated circuits are characterized according to net type. Each net type has one or more mask registers that drive control inputs to each boundary scan register that drives a net of that type. One integrated circuit is configured to drive, while the others are configured to receive. The boundary scan registers are initialized to predetermined values, the mask registers are loaded, and clocks are pulsed to perform the needed tests. The results are then scanned out of the boundary scan registers, and a compression circuit compresses the test results data.