Patents by Inventor Frank Worrell

Frank Worrell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6877082
    Abstract: A disclosed address generation system includes a decrementer and a multiplexer. The decrementer produces a decremented address signal by subtracting a first integer value from an incremented address signal. The multiplexer produces either the incremented address signal or the decremented address signal dependent upon a control signal. A described instruction fetch apparatus includes an instruction queuing and selection subsystem producing either an even portion or an odd portion of an instruction data block, specified by a first address signal, as a fetched instruction dependent upon one or more control signals generated based on determining bits of second and third address signals. A disclosed central processing unit (CPU) includes an instruction cache and a processor core, wherein the processor core includes an address generation subsystem generating the first, second, and third address signals, and the instruction queuing and selection subsystem. A method is described for fetching an instruction.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: April 5, 2005
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 6728816
    Abstract: A circuit that may be used with a split transaction bus. The circuit generally comprises a register logic and a compare logic. The register logic may be configured to (i) present a first identification signal associated with a first slave device to perform a first transaction and (ii) store a second identification signal associated with a second slave device in place of the first identification signal responsive to a ready signal presented by the second slave device. The compare logic may be configured to (i) compare the second identification signal with the first identification signal and (ii) present a back off signal responsive to the compare.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 6671781
    Abstract: A circuit comprising a cache memory, a memory management unit and a logic circuit. The cache memory may be configured as a plurality of associative sets. The memory management unit may be configured to determine a data tag from an address of a data item. The logic circuit may be configured to (i) determine a selected set from the plurality of associative sets that produces a cache-hit for the data tag, (ii) buffer the address and the data item during a cycle, and (iii) present the data item to the cache memory for storing in the selected set during a subsequent cycle.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: December 30, 2003
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Publication number: 20030191896
    Abstract: A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 9, 2003
    Inventors: Frank Worrell, Gagan V. Gupta
  • Patent number: 6584537
    Abstract: A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: June 24, 2003
    Assignee: LSI Logic Corporation
    Inventors: Frank Worrell, Gagan V. Gupta
  • Patent number: 6412066
    Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: June 25, 2002
    Assignee: LSI Logic Corporation
    Inventors: Frank Worrell, Hartvig Ekner
  • Publication number: 20020066006
    Abstract: A method of conditional branching in a pipelined processor. The method comprising the steps of (A) prefetching a branch target address in response to encountering a branch instruction, in prediction of taking a branch, and (B) evaluating between (i) taking the branch and (ii) not taking the branch substantially contemporaneously with prefetching the branch target address.
    Type: Application
    Filed: November 29, 2000
    Publication date: May 30, 2002
    Applicant: LSI LOGIC CORPORATION
    Inventor: Frank Worrell
  • Publication number: 20010029577
    Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.
    Type: Application
    Filed: April 5, 2001
    Publication date: October 11, 2001
    Applicant: LSI Logic Corporation
    Inventors: Frank Worrell, Hartvig Ekner
  • Publication number: 20010025337
    Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.
    Type: Application
    Filed: April 3, 2001
    Publication date: September 27, 2001
    Inventors: Frank Worrell, Hartvig Ekner
  • Patent number: 6012138
    Abstract: A processor for a data-processing system is provided with a dynamically reconfigurable multistage pipeline which permits the execution of more than one instruction set by the processor utilizing the same instruction decoding circuitry and instruction execution control logic circuitry. In one embodiment, the pipeline includes an instruction fetch stage, an instruction conversion stage, an instruction decode stage, and a multiplexer which is used to switch the instruction conversion stage into and out of the pipeline between the instruction fetch stage and the instruction decode stage, even while instructions continue to be executed by the pipeline. The multiplexer operates under control of the instruction decode stage and may be set in response to decoded instructions. The instruction fetch stage is coupled to a bus to retrieve an instruction at a location specified by a program counter.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: January 4, 2000
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5982194
    Abstract: A technique for designing circuits with arithmetic or logic functions on integrated circuit devices. The circuit has a primary chain of serially connected logic blocks and secondary chains of serially connected logic blocks. The output node of the last logic block of each secondary chain is connected to an input node of a logic block in the primary chain. Depending upon the desired function, the logic blocks can be logic gates or more complex logic blocks. Zero detect and compare circuits can be designed from this basic arrangement. Connected with input logic, output logic and merge logic, other circuits, including incrementors, decrementors, priority logic, adders and ALUs, are possible. The resulting circuit occupies far less space on an integrated circuit than a fully parallel, lookahead circuit, yet operating speeds are comparable.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: November 9, 1999
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5931941
    Abstract: A way of designing CPU's and computational units in an integrated circuit so that the computational unit can be designed and connected to the CPU in a modular manner. The computational unit designed for one application can be redesigned for another application without requiring a change in the CPU. The CPU has an instruction register, a first decoder connected to the instruction register to decode instruction words within a predefined set of instructions, an ALU, and buses which move operand data into the ALU and results data from the ALU. The ALU operates and the buses function responsive to the first decoder. The computational unit has an execution unit connected in parallel with the ALU to the buses, and a second decoder connected to the instruction register. The second decoder decodes only a predetermined portion of an instruction word in the instruction register when the instruction word is not in the predefined set of instructions. The execution unit operates responsive to the second decoder.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5905893
    Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: May 18, 1999
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5896519
    Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: April 20, 1999
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5867681
    Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The decompression of the immediate field used for load/store instructions having the global pointer register as a base register is optimized for mixed compressed/non-compressed instruction execution. The immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: February 2, 1999
    Assignee: LSI Logic Corporation
    Inventors: Frank Worrell, Hartvig Ekner
  • Patent number: 5794010
    Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: August 11, 1998
    Assignee: LSI Logic Corporation
    Inventors: Frank Worrell, Hartvig Ekner
  • Patent number: 5784634
    Abstract: An integrated circuit CPU is provided. The CPU has a program counter register; an instruction register; an instruction decoder connected directly to the instruction register; a register file responsive to control signals from the instruction decoder; an ALU operating upon data from the register file and generating results responsive to the control signals; and a result register that holds results while the results are written back to the register file. The CPU has only three pipelined stages of operation. The three stages comprise fetching an instruction from the memory subsystem into the instruction register; executing an instruction in the instruction register; and writing back results in the result register to the register file. Operating speeds are comparable to CPUs with a greater number of stages.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: July 21, 1998
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5774709
    Abstract: The handling of branch delay slots in MIPS microprocessors is enhanced. Branch instructions can be placed in branch delay slots by the judicious operation of the Exception Pointer Counter and the BD bit in the Cause register for exception handling.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: June 30, 1998
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5729482
    Abstract: A shifter design which is useful in microprocessors is presented. The shifter can perform the operations of a shift right, shift left and shift right arithmetic in which the sign bit of the shifted data word is replicated into the vacated bit positions caused by the shift to the right. The shifter has a rotation count unit, a rotation unit, a mask decoder unit and a logic unit for high-speed operation and occupies a minimal amount of area in an integrated circuit.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: March 17, 1998
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Patent number: 5670900
    Abstract: A complex, say, N=5 or greater input terminal, mask decoder circuit which is useful in the design of ALUs in microprocessors is presented. The circuit avoids wiring and uses logic gates to make the connections between the input terminals receiving the control bit signals and the output terminals on which the mask signals are generated. This allows the mask decoder circuit to occupy a minimal amount of space on an integrated circuit.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: September 23, 1997
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell