Abstract: A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.

Abstract: A synchronous memory device includes a distributed FIFO buffer in a read path. Buffer stages of the FIFO are located at remote ends of an internal data bus. The time needed for loading the first FIFO stage is reduced and allows shorter clock cycle times for some memory read operations.

Abstract: A memory and system reduce power consumption by reducing a power supply level. The memory includes input circuitry coupled to a data communication bus. The input circuitry has first and second threshold detection levels to detect voltage transitions of data signals communicated on the bus. The memory device changes threshold voltage detection levels in synchronization with other memories coupled to the bus. In one embodiment, the synchronization is performed while the memory devices are in a power down state. A power supply provided to the memory device is changed while the memory is in the power-down state.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original manufacturer information. The integrated circuit can be a memory device and allows the user to upgrade a system while indicating to the original system that the device is compatible.

Abstract: A memory device includes memory cells arranged in multiple blocks. A register is provided to track multiple open pages per block of the memory. In one embodiment, the register is located in the memory device and used to determine if a memory access is to be performed. In another embodiment, the register is located external to the memory and used by a processor and/or chip set to determine if an access request is needed.

Abstract: Power consumption by a memory device is optimized by maintaining data input buffers in an off state until a command sequence containing a write command is received by the memory. A software command sequence is provided to the memory device where the software command sequence was constructed by generating a command sequence of n cycles and providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, where m is less than n. The data input buffers are returned to an off state upon completion of a program or erase operation defined in the received command sequence.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. A double data rate interface is provided to allow data to be input and output from the memory in synchronization with both rising and falling edges of a clock signal.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: A synchronous memory device includes a distributed FIFO buffer in a read path. Buffer stages of the FIFO are located at remote ends of an internal data bus. The time needed for loading the first FIFO stage is reduced and allows shorter clock cycle times for some memory read operations.

Abstract: A flash memory has erase blocks aligned primarily with array rows and secondarily with array rows. This architecture allows data to be stored across numerous pages without risking accidental erasure caused by crossing multiple erase blocks. As a result, non-volatile memory devices to be more easily substituted for volatile memory devices. In one embodiment, a flash memory includes an array of memory cells that have a plurality of adjacent pages. Addresses of the memory cells are scrambled within the pages to define erase blocks that cross the page boundaries.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.

Abstract: An integrated circuit includes a delay lock circuit to synchronize an internal clock signal with an external clock. The integrated circuit, in one embodiment, is a memory device. The delay lock circuit includes a delay line, a delay register to control a delay time of the delay line, and a non-volatile register. The non-volatile register stores an initial value for the delay register. The delay register is pre-loaded with the contents of the non-volatile register to decrease the time need to synchronize the clock signals.

Abstract: A flash memory device having a mini array to store operating parameters. In one embodiment, the flash memory device comprises at least one array block of memory, one or more local latches to store one or more operating parameters and a mini array of non-volatile memory cells. The mini array is used to store the one or more operating parameters. During operation of the flash memory device, the one or more operating parameters are retrieved from the mini array and stored in associated local latches.

Abstract: A flash memory device having a mini array to store operating parameters. In one embodiment, the flash memory device comprises at least one array block of memory, one or more local latches to store one or more operating parameters and a mini array of non-volatile memory cells. The mini array is used to store the one or more operating parameters. During operation of the flash memory device, the one or more operating parameters are retrieved from the mini array and stored in associated local latches.

Abstract: A non-volatile memory device having separate read and write paths. In one embodiment, a flash memory device has a memory array, a first multiplexer and a second multiplexer. The memory array has non-volatile memory cells arranged in columns and rows. Each memory cell in a column is coupled to an associated bit line. The first multiplexer is coupled to select bit lines during write operations to the memory array. The second multiplexer is coupled to select bit lines during read operations from the memory array.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: A state machine and an associated method for achieving a faster response time for an interruption of an erase operation in a flash memory are disclosed. In particular, a state machine having a plurality of interconnected execution cycles is disclosed. The execution cycles include incremental cycles and other cycles. The state machine also includes a plurality of suspend cycles. Each suspend cycle is connected directly to one of the execution cycles. At least one of the suspend cycles is connected directly to one of the other cycles. The plurality of suspend cycles interrupt the erase operation in response to a suspend command by adjusting one shot timing circuits, timer counters, and timing circuits included in the state machine. The state machine may include a plurality of interconnected groups, each having a plurality of execution cycles.