Patents by Inventor Frederic Allibert
Frederic Allibert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160372484Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency, RF, circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.Type: ApplicationFiled: June 8, 2016Publication date: December 22, 2016Inventors: Bich-Yen Nguyen, Frederic Allibert, Christophe Maleville
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Patent number: 9443933Abstract: The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor (43) of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor (44) of the other transistor of said transistor pair by a distance D less than half the transistor channel width, said distance d between two sub-transistors (43, 44) being measured between the respective center of the channels of said sub-transistors.Type: GrantFiled: August 13, 2013Date of Patent: September 13, 2016Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Frédéric Allibert, Maud Vinet
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Publication number: 20150325686Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.Type: ApplicationFiled: May 8, 2014Publication date: November 12, 2015Applicants: STMICROELECTRONICS, INC., SOITECInventors: Frédéric Allibert, Pierre Morin
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Manufacturing method for a semiconductor on insulator type substrate for radiofrequency applications
Patent number: 9129800Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radio frequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate with an electrical resistivity of more than 500 Ohm.cm, (b) formation of a polycrystalline silicon layer on the substrate, the method comprising a step between steps a) and b) to form a dielectric material layer, different from a native oxide layer, on the substrate, between 0.5 and 10 nm thick.Type: GrantFiled: March 22, 2012Date of Patent: September 8, 2015Assignees: Soitec, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Frédéric Allibert, Julie Widiez -
Publication number: 20150221723Abstract: The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor (43) of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor (44) of the other transistor of said transistor pair by a distance D less than half the transistor channel width, said distance d between two sub-transistors (43, 44) being measured between the respective center of the channels of said sub-transistors.Type: ApplicationFiled: August 13, 2013Publication date: August 6, 2015Applicant: Commissariat à I'Energie Atomique et aux Energies AlternativesInventors: Frédéric Allibert, Maud Vinet
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Patent number: 9076713Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localized positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.Type: GrantFiled: January 23, 2013Date of Patent: July 7, 2015Assignees: Soitec, Commissariat à l'Énergie AtomiqueInventors: Thomas Signamarcheix, Frederic Allibert, Chrystel Deguet
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Publication number: 20150168326Abstract: The invention relates to a method for testing a semiconductor substrate (1) for radiofrequency applications, characterized in that the electrical resistivity profile of the substrate as a function of depth, is measured and, using the profile, a criterion is calculated, defined by the formula (I): where D is the integration depth, ?(x) is the electrical conductivity measured at a depth x in the substrate, and L is a characteristic attenuation length of the electric field in the substrate. The invention also relates to a method for selecting a semiconductor substrate (1) for radiofrequency applications and to a device for implementing these methods.Type: ApplicationFiled: January 15, 2013Publication date: June 18, 2015Applicant: SOITECInventor: Frederic Allibert
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Publication number: 20140225182Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: SoitecInventors: Mohamad A. Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
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Patent number: 8802539Abstract: The present invention relates to a process for preparing semiconductor-on-insulator type structures that include a semiconductor layer of a donor substrate, an insulator layer and a receiver substrate. The process includes bonding of the donor substrate onto the receiver substrate, with at least one of the substrates being coated with an insulator layer, and forming at the bonding interface a so-called trapping interface of electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor-on-insulator type structure that includes such a trapping interface.Type: GrantFiled: July 21, 2008Date of Patent: August 12, 2014Assignee: SoitecInventors: Frédéric Allibert, Sébastien Kerdiles
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Patent number: 8765571Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.Type: GrantFiled: March 21, 2012Date of Patent: July 1, 2014Assignee: SoitecInventors: Oleg Kononchuk, Frederic Allibert
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Patent number: 8735946Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: GrantFiled: September 16, 2013Date of Patent: May 27, 2014Assignee: SoitecInventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
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MANUFACTURING METHOD FOR A SEMICONDUCTOR ON INSULATOR TYPE SUBSTRATE FOR RADIOFREQUENCY APPLICATIONS
Publication number: 20140084290Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radiofrequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate (1) with an electrical resistivity of more than 500 Ohm·cm, (b) formation of a polycrystalline silicon layer (4) on said substrate (1), said method comprising a step between steps a) and b) to form a dielectric material layer (5), different from a native oxide layer, on the substrate (1), between 0.5 and 10 nm thick.Type: ApplicationFiled: March 22, 2012Publication date: March 27, 2014Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, SoitecInventors: Frédéric Allibert, Julie Widiez -
Publication number: 20140015023Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: SoitecInventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure, Mohamad A. Shaheen
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Patent number: 8535996Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: GrantFiled: March 13, 2008Date of Patent: September 17, 2013Assignee: SOITECInventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
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Patent number: 8372733Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.Type: GrantFiled: September 2, 2009Date of Patent: February 12, 2013Assignees: Soitec, Commissariat à l'Énergie AtomiqueInventors: Thomas Signamarcheix, Frederic Allibert, Chrystel Deguet
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Publication number: 20120244687Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.Type: ApplicationFiled: March 21, 2012Publication date: September 27, 2012Applicant: SOITECInventors: Oleg Kononchuk, Frederic Allibert
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Patent number: 8153504Abstract: The invention relates to a process for manufacturing a composite substrate comprising bonding a first substrate onto a second semiconducting substrate, characterized in that the process includes, before bonding, the formation of a bonding layer between the first and the second substrate, the bonding layer comprising a plurality of islands distributed over a surface of the first substrate in a determined pattern and separated from one another by regions of a different type, which are distributed in a complementary pattern, wherein the islands are formed via a plasma treatment of the material of the first substrate.Type: GrantFiled: March 26, 2008Date of Patent: April 10, 2012Assignee: SoitecInventors: Frederic Allibert, Sebastien Kerdiles
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Patent number: 8008929Abstract: An apparatus for measuring a lifetime of charge carriers that has a measuring probe and a component for directing ultraviolet radiation to a measuring position. The measuring probe also includes at least one electrode provided at a predetermined spatial relationship to the measuring position. A microwave source is adapted to direct microwave radiation to the measuring position, a microwave detector is adapted to measure an alteration of an intensity of microwave radiation reflected at the measuring position in response to the ultraviolet radiation and a semiconductor structure holder is adapted to receive a semiconductor structure and to provide an electric contact to a portion of the semiconductor structure. Additionally, a device for moving the substrate holder relative to the measuring probe is provided for positioning at least one portion of the semiconductor structure at the measuring position.Type: GrantFiled: September 8, 2008Date of Patent: August 30, 2011Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Frederic Allibert, Oleg Kononchuk
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Patent number: 7977747Abstract: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding; providing plasma activation energy in an amount sufficient to activate a portion of the thickness of the face of the first insulating layer emp1 and a portion of the thickness of the face of the second insulating layer emp1; providing a final insulating layer by molecular bonding the activated face of the first insulating layer with the activated face of the second insulating layer; and removing a back portion of the source substrate while retaining an active layer comprising a remaining portion of the source substrate bonded to the support substrate with the final insulating layer interposed therein to form the composite substrate.Type: GrantFiled: February 18, 2010Date of Patent: July 12, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Frédéric Allibert, Sébastien Kerdiles
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Publication number: 20110012200Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: ApplicationFiled: March 13, 2008Publication date: January 20, 2011Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Mohamad Shaheen, Carlos Mazure