Patents by Inventor Frederick Perner

Frederick Perner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8971091
    Abstract: A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 3, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Yi, Muhammad Shakeel Qureshi, Frederick Perner, Richard Carter
  • Patent number: 8942026
    Abstract: A read circuit for sensing a resistive state of a resistive switching device in a crosspoint array has an equipotential preamplifier connected to a selected column line of the resistive switching device in the array to deliver a read current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit includes a reference voltage generation component for generating the reference voltage for the equipotential preamplifier. The reference voltage generation component samples the biasing voltage via the selected column line and adds a small increment to a sampled biasing voltage to form the reference voltage.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: January 27, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick Perner
  • Patent number: 8933431
    Abstract: A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments. A plurality of memory cells in an upper plane of the memory array are formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures, and a plurality of memory cells in a lower plane are formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: January 13, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick Perner
  • Publication number: 20140379977
    Abstract: Dynamic/static random access memory (D/SRAM) cell, block shift static random access memory (BS-SRAM) and method using the same employ dynamic storage mode and dynamic storage mode switching to shift data. The D/SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, and a dynamic/static (D/S) mode selector to selectably switch the D/SRAM cell between the dynamic storage mode and a static storage mode. The BS-SRAM includes a plurality of D/SRAM cells arranged in an array and a controller to shift data from an adjacent D/SRAM cell in a second row of the array to a D/SRAM cell in a first row. The method includes switching the mode of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected D/SRAM cell.
    Type: Application
    Filed: January 30, 2012
    Publication date: December 25, 2014
    Inventor: Frederick A. Perner
  • Publication number: 20140359209
    Abstract: Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.
    Type: Application
    Filed: January 30, 2012
    Publication date: December 4, 2014
    Inventors: Frederick A. Perner, Matthew D. Pickett
  • Publication number: 20140347910
    Abstract: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric current sensed from the target memory element when the target memory element is fully selected.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick Perner
  • Publication number: 20140215143
    Abstract: Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D. Pickett, Frederick Perner
  • Publication number: 20140204651
    Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and outputting a current with said current mirror.
    Type: Application
    Filed: October 8, 2013
    Publication date: July 24, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick Perner
  • Publication number: 20140198559
    Abstract: A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes a transimpedance equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. A reference resistor is selectively connected to the equipotential preamplifier for setting a reference current, wherein the equipotential preamplifier is set to produce a preamplifier output voltage having a magnitude depending on whether the sense current is smaller or greater than the reference current. A voltage comparator is connected to the equipotential preamplifier to compare the preamplifier output voltage with a setup reference voltage and generate a comparator output voltage indicative of the resistance state of the resistive switching device.
    Type: Application
    Filed: August 26, 2011
    Publication date: July 17, 2014
    Inventor: Frederick Perner
  • Patent number: 8780613
    Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and outputting a current with said current mirror.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: July 15, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick Perner
  • Publication number: 20140153318
    Abstract: A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes an equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit has a reference current source for generating a sense reference current, and a current comparator connected to evaluate the sense current delivered by the equipotential preamplifier against the sense reference current and generating an output signal indicative of the resistance state of the resistive switching device.
    Type: Application
    Filed: July 22, 2011
    Publication date: June 5, 2014
    Inventor: Frederick Perner
  • Publication number: 20140014891
    Abstract: A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments. A plurality of memory cells in an upper plane of the memory array are formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures, and a plurality of memory cells in a lower plane are formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.
    Type: Application
    Filed: March 29, 2011
    Publication date: January 16, 2014
    Inventor: Frederick Perner
  • Patent number: 8611133
    Abstract: A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: December 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D. Pickett, Frederick A. Perner, R. Stanley Williams
  • Patent number: 8570785
    Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: October 29, 2013
    Assignee: Hewlett-Packard Development Company
    Inventor: Frederick Perner
  • Patent number: 8542515
    Abstract: A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 24, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick Perner
  • Publication number: 20130235651
    Abstract: A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.
    Type: Application
    Filed: January 31, 2011
    Publication date: September 12, 2013
    Inventors: Frederick Perner, Wei Yi, Matthew D. Pickett
  • Publication number: 20130223132
    Abstract: A read circuit for sensing a resistive state of a resistive switching device in a crosspoint array has an equipotential preamplifier connected to a selected column line of the resistive switching device in the array to deliver a read current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit includes a reference voltage generation component for generating the reference voltage for the equipotential preamplifier. The reference voltage generation component samples the biasing voltage via the selected column line and adds a small increment to a sampled biasing voltage to form the reference voltage.
    Type: Application
    Filed: February 28, 2011
    Publication date: August 29, 2013
    Inventor: Frederick Perner
  • Publication number: 20130223134
    Abstract: A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 29, 2013
    Inventors: Wei Yi, Muhammad Chakeel Qureshi, Frederick Perner, Richard Carter
  • Publication number: 20130207069
    Abstract: A metal-insulator transition switching device includes a first electrode and a second electrode. A channel region which includes a bulk metal-insulator transition material separates the first electrode and the second electrode. A method for forming a metal-insulator transition switching device includes depositing a layer of bulk metal-insulator transition material in between a first electrode and a second electrode to form a channel region and forming a gate electrode operatively connected to the channel region.
    Type: Application
    Filed: October 21, 2010
    Publication date: August 15, 2013
    Inventors: Matthew D. Pickett, Philip J. Kuekes, R. Stanley Williams, Frederick Perner, Wei Wu, Alexandre M. Bratkovski
  • Publication number: 20130176766
    Abstract: A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Inventors: Matthew D. Pickett, Frederick A. Perner, R. Stanley Williams