Abstract: Three-dimensional (3D) memory structures and methods of formation of same are provided herein. In some embodiments, a 3D memory fabrication structure includes: a base silicon (Si) layer; a silicon germanium (SiGe) layer disposed above the base Si layer; and a doped silicon (Si) layer disposed on at least one side of the SiGe layer, wherein the doped Si layer contains a dopant that is at least one of carbon (C) or boron (B).

Abstract: Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate, planarizing the substrate to the CMP stop layer, removing a portion of a top of the two Si walls and forming an L-pad formation, deep etching a pattern of holes into the space between the two Si walls in horizontal portions of the plurality of alternating Si layers and SiGe layers, and forming vertical wordline structures from the pattern of holes in the horizontal portions.

Abstract: Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

Abstract: Methods of forming a three-dimensional dynamic random-access memory (3D DRAM) structure are provided herein. In some embodiments, a method of forming a 3D DRAM structure includes forming at least one wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises: vertically etching a first pattern of holes; filling the first pattern of holes with a silicon germanium fill; vertically etching a plurality of isolation slots through the first stack; filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill; etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and depositing a layer of conductive material that wraps around the plurality of gate silicon channels.

Abstract: Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate, planarizing the substrate to the CMP stop layer, removing a portion of a top of the two Si walls and forming an L-pad formation, deep etching a pattern of holes into the space between the two Si walls in horizontal portions of the plurality of alternating Si layers and SiGe layers, and forming vertical wordline structures from the pattern of holes in the horizontal portions.

Abstract: Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features.

Abstract: Systems and methods using a three-dimensional memory device with a number of memory cells disposed vertically in a number of pillars arranged along a horizontal direction can be used in a variety of applications. In various embodiments, pillars of memory cells may be disposed between lower and upper digitlines respectively coupled to different sense amplifiers to provide read/write operations and refresh operations. In various embodiments, a three-dimensional memory device having an array of memory cells vertically arranged in pillars may include a sense amplifier and digitline with a static random access memory cache, where the static random access memory cache is disposed below the array of memory cells in the same die. Additional apparatus, systems, and methods are disclosed.

Abstract: Systems and methods using a three-dimensional memory device with a number of memory cells disposed vertically in a number of pillars arranged along a horizontal direction can be used in a variety of applications. In various embodiments, pillars of memory cells may be disposed between lower and upper digitlines respectively coupled to different sense amplifiers to provide read/write operations and refresh operations. In various embodiments, a three-dimensional memory device having an array of memory cells vertically arranged in pillars may include a sense amplifier and digitline with a static random access memory cache, where the static random access memory cache is disposed below the array of memory cells in the same die. Additional apparatus, systems, and methods are disclosed.

Abstract: A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide.

Abstract: A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide.