Patents by Inventor Fritz A. Boehm

Fritz A. Boehm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9448872
    Abstract: Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: September 20, 2016
    Assignee: Apple Inc.
    Inventors: Ben D. Jarrett, Fritz A. Boehm
  • Publication number: 20150227410
    Abstract: Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 13, 2015
    Applicant: Apple Inc.
    Inventors: Ben D. Jarrett, Fritz A. Boehm
  • Patent number: 8869080
    Abstract: An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: October 21, 2014
    Assignee: Apple Inc.
    Inventors: Edmond R. Bures, Fritz A. Boehm
  • Publication number: 20140100841
    Abstract: A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: APPLE INC.
    Inventors: Edmond R. Bures, Jeffrey V. Lent, Fritz A. Boehm
  • Publication number: 20140089873
    Abstract: An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Applicant: APPLE INC.
    Inventors: Edmond R. Bures, Fritz A. Boehm
  • Patent number: 8650519
    Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 11, 2014
    Assignee: Apple Inc.
    Inventor: Fritz A. Boehm
  • Patent number: 8543953
    Abstract: A method is contemplated in which the stimulus to an IC design simulation may be automatically manipulated or steered so that the test environment is altered during subsequent simulations of the IC design based upon the simulation results and/or configuration settings of previous simulations of the IC design. More particularly, a stimulation steering tool may analyze the simulation results and/or the test environment, and manipulate the test environment, which may include the test generator output, and the test bench model, for subsequent simulations.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: September 24, 2013
    Assignee: Apple Inc.
    Inventor: Fritz A. Boehm
  • Publication number: 20130174108
    Abstract: A method is contemplated in which the stimulus to an IC design simulation may be automatically manipulated or steered so that the test environment is altered during subsequent simulations of the IC design based upon the simulation results and/or configuration settings of previous simulations of the IC design. More particularly, a stimulation steering tool may analyze the simulation results and/or the test environment, and manipulate the test environment, which may include the test generator output, and the test bench model, for subsequent simulations.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Inventor: Fritz A. Boehm
  • Patent number: 8429581
    Abstract: A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a simulation stimulus on a test bench and saving the simulation output. The reference IC design corresponds to an IC design model having visibility to comprehensive internal device state. The method may also include simulating a modified version of the reference IC design using the same simulation stimulus on the same test bench, and saving the modified version simulation output. In addition, the simulation outputs of the reference IC design and the modified version are compared to create a comparison result. Lastly, the method may include determining whether the modified version of the reference IC design is functionally equivalent to the reference IC design based upon the comparison result.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: April 23, 2013
    Assignee: Apple Inc.
    Inventor: Fritz A. Boehm
  • Publication number: 20130061191
    Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Inventor: Fritz A. Boehm
  • Publication number: 20130061190
    Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, if an event is detected on a speed path, the endpoint of that speed path may be forced to a failing value, and the simulation may be resumed. At some point later in the simulation, the simulation results may be checked to determine if a failure that corresponds to the failing value was observed at a structure that would be visible on a manufactured version of the IC design. If the failure is visible, the test vectors that were used may be identified and captured for use in production testing.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Inventor: Fritz A. Boehm
  • Patent number: 8392860
    Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, if an event is detected on a speed path, the endpoint of that speed path may be forced to a failing value, and the simulation may be resumed. At some point later in the simulation, the simulation results may be checked to determine if a failure that corresponds to the failing value was observed at a structure that would be visible on a manufactured version of the IC design. If the failure is visible, the test vectors that were used may be identified and captured for use in production testing.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: March 5, 2013
    Assignee: Apple Inc.
    Inventor: Fritz A. Boehm
  • Publication number: 20130055174
    Abstract: A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a simulation stimulus on a test bench and saving the simulation output. The reference IC design corresponds to an IC design model having visibility to comprehensive internal device state. The method may also include simulating a modified version of the reference IC design using the same simulation stimulus on the same test bench, and saving the modified version simulation output. In addition, the simulation outputs of the reference IC design and the modified version are compared to create a comparison result. Lastly, the method may include determining whether the modified version of the reference IC design is functionally equivalent to the reference IC design based upon the comparison result.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Inventor: Fritz A. Boehm
  • Patent number: 7346484
    Abstract: The monitor manager manages the execution of monitors during the simulation of a digital design. The monitor manager (20) includes an instance generator (32) that creates executable instances (38) of monitors that may be time-dependent monitors, an activation manager (34) that assigns instances to be active or inactive, and an execution unit (36) that executes active instances and receives returned status values passed, failed, active, or error. Executable instances of time-dependent monitors are software state machines having a state variable, one or more time-dependent variables, and at least two state-driven code blocks, at least one of which might be either a cycle-dependent code block that tests for a specific cycle-dependent condition, or an event-dependent code block that tests for a specific event-dependent condition. In either case, the state-driven code block increments the time-dependent variable, and, when the condition has been satisfied, increments the state variable.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: March 18, 2008
    Assignee: Intrinsity, Inc.
    Inventor: Fritz A. Boehm
  • Patent number: 7299461
    Abstract: An expansion syntax that creates a set of expressions in software code is disclosed. The syntax includes one or more expansion constructs embedded within a software code expression, interpreted by an expansion function to create a set of expanded expressions. Each construct includes an expansion syntax indicator and a plurality of list parameters, which may be start, end, step, and skip integers, or strings of non-white space. Both constructs may include either default or expressly assigned list names, which serve as iterators during the expansion process. Each expanded expression created includes a list member from each embedded construct. The expansion methodology, and the resulting set of expanded expressions, depends upon the number of unique iterators present in the software code expression and whether any of the embedded constructs include the stride parameter.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: November 20, 2007
    Assignee: Intrinsity, Inc.
    Inventors: Fritz A. Boehm, Terence M. Potter, James S. Blomgren
  • Patent number: 7099812
    Abstract: The disclosed invention is a grid that monitors a design simulation to support design verification coverage analysis. The disclosed invention includes n ordered axis declarations 72 that each correspond to a functional attribute and list at least two valid functional states, logic expressions 78 that test for the functional states and set axis variables, and a grid declaration 80 that converts the axis variables to a unique linear index value corresponding to the cross-product of the achieved functional states and records hits. The linear index is calculated by multiplying the integer value of each axis variable (except the nth axis variable) by the product of the sizes of each higher-order axis than the axis to which said axis variable corresponds, summing the results, and adding the integer value of the nth said axis variable.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 29, 2006
    Assignee: Intrinsity, Inc.
    Inventor: Fritz A. Boehm
  • Patent number: 7031897
    Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: April 18, 2006
    Assignee: Intrinsity, Inc.
    Inventors: James S. Blomgren, Fritz A. Boehm
  • Patent number: 6889180
    Abstract: The present invention is a monitor that detects a design verification event and reports a status event to a database. One embodiment of the present invention comprises a monitor declaration, zero or more signal declarations, zero or more bus declarations and one or more logic expressions. A logic expression, formulated using the declared signals and buses, is used to evaluate whether a specific verification event has occurred. The present invention further comprises a monitor where the signal of the signal declaration of the monitor is an N-Nary signal. Additionally, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: May 3, 2005
    Assignee: Intrinsity, Inc.
    Inventors: Laura A. Weber, Fritz A. Boehm, Jean Anne Booth, Jeffrey S. Leonard, Shawn D. Strawbridge, Douglas N. Good
  • Publication number: 20040139423
    Abstract: An expansion syntax that creates a set of expressions in software code is disclosed. The syntax includes one or more expansion constructs embedded within a software code expression, interpreted by an expansion function to create a set of expanded expressions. Each construct includes an expansion syntax indicator and a plurality of list parameters, which may be start, end, step, and skip integers, or strings of nonwhite space. Both constructs may include either default or expressly assigned list names, which serve as iterators during the expansion process. Each expanded expression created includes a list member from each embedded construct. The expansion methodology, and the resulting set of expanded expressions, depends upon the number of unique iterators present in the software code expression and whether any of the embedded constructs include the stride parameter.
    Type: Application
    Filed: December 16, 2003
    Publication date: July 15, 2004
    Applicant: Intrinsity, Inc.
    Inventors: Fritz A. Boehm, Terence M. Potter, James S. Blomgren
  • Patent number: 6728654
    Abstract: A random number indexing method and apparatus includes an index array 302 that uniquely identifies each pseudo-random number in a sequence of numbers generated by a pseudo-random number generator 202. A computer program 102 provides a seed value to the pseudo-random number generator and populates the index array. The computer program uses the identifying indicia in the index array to call for and receive pseudo-random numbers.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 27, 2004
    Assignee: Intrinsity, Inc.
    Inventor: Fritz A. Boehm