Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

Abstract: An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions.

Abstract: A method for performing manual operations, such as address compare equal stop, single cycle alter, etc., in a time slice controlled microprocessor with microprogramming, which avoids stopping the processor clock when any of the programs requires a manual operation. This problem is solved by assigning the manual operations to a specific program, which for the other programs in the multiprogram environment executes the manual operations required.

Abstract: For increasing the availability of a modular computer, a control unit and switches are provided, the latter being connected in between the control storages and the remaining identical hardware of the processor. In the case of a hardware error of one processor, its control storage is switched for a specific period of time to the same hardware of another processor which interrupts its own tasks, assuming the tasks of the defective processor for the time during which the control storage of the defective processor remains switched off. Subsequently, the former or non-defective processor resumes its own tasks. The task cycles assigned to one processor or the other can be specified to be identical or as a function of the respective processing requirements.