Patents by Inventor Fufa Chen

Fufa Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8580042
    Abstract: An apparatus for cleaning and conditioning the surface of a semiconductor substrate such as wafer includes a rotatable chuck, a chamber, a rotatable tray for collecting cleaning solution with one or more drain outlets, multiple receptors for collecting multiple cleaning solutions, a first motor to drive chuck, and a second motor to drive the tray. The drain outlet in the tray can be positioned directly above its designated receptor located under the drain outlet. The cleaning solution collected by the tray can be guided into designated receptor. One characteristic of the apparatus is having a robust and precisely controlled cleaning solution recycle with minimum cross contamination.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: November 12, 2013
    Assignee: ACM Research (Shanghai) Inc.
    Inventors: Voha Nuch, David Wang, Yue Ma, Fufa Chen, Jian Wang, Yunwen Huang, Liangzhi Xie, Chuan He
  • Publication number: 20110114120
    Abstract: An apparatus for cleaning and conditioning the surface of a semiconductor substrate such as wafer includes a rotatable chuck, a chamber, a rotatable tray for collecting cleaning solution with one or more drain outlets, multiple receptors for collecting multiple cleaning solutions, a first motor to drive chuck, and a second motor to drive the tray. The drain outlet in the tray can be positioned directly above its designated receptor located under the drain outlet. The cleaning solution collected by the tray can be guided into designated receptor. One characteristic of the apparatus is having a robust and precisely controlled cleaning solution recycle with minimum cross contamination.
    Type: Application
    Filed: December 10, 2007
    Publication date: May 19, 2011
    Inventors: Voha Nuch, David Wang, Yue Ma, Fufa Chen, Jian Wang, Yunwen Huang, Liangzhi Xie, Chuan He
  • Patent number: 6660135
    Abstract: A semiconductor metallization process for providing complete via fill on a substrate, free of voids, and a planar metal surface, free of grooves. In one aspect, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A conformal PVD metal layer, such as Al or Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr. The vias and/or contacts are then filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably performed in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by at least 100 mm, and a hot metal PVD chamber, also serving as a reflow chamber.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: December 9, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Sang-Ho Yu, Yonghwa Chris Cha, Murali Abburi, Shri Singhvi, Fufa Chen
  • Publication number: 20020114886
    Abstract: A method of forming a titanium silicide nitride (TiSiN) layer is described. A titanium nitride (TiN) layer is deposited on a substrate, the process chamber is purged to remove reaction by-products therefrom and than the titanium nitride (TiN) layer is exposed to a silicon-containing gas to form the titanium suicide nitride (TiSiN) layer. Alternatively, the substrate may be exposed to the silicon-containing gas in a process chamber different from the one used for the titanium nitride (TiN) layer deposition.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 22, 2002
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Jing-Pei Chou, Chien-Teh Kao, Chiukin Steven Lai, Roderick Craig Mosely, Mei Chang, Fufa Chen
  • Patent number: 6436820
    Abstract: The present disclosure pertains to the discovery that TiN films having a thickness of greater than about 400 Å and, particularly greater than 1000 Å, and a resistivity of less than about 175 &mgr;&OHgr;cm, can be produced by a CVD technique in which a series of TiN layers are deposited to form a desired TiN film thickness. Each layer is deposited employing a CVD deposition/treatment step. During a treatment step, residual halogen (typically chlorine) was removed from the CVD deposited film. Specifically, a TiN film having a thickness of greater than about 400 Å was prepared by a multi deposition/treatment step process where individual TiN layers having a thickness of less than 400 Å were produced in series to provide a finished TiN layer having a combined desired thickness. Each individual TiN layer was CVD deposited and then treated by exposing the TiN surface to ammonia in an annealing step carried out in an ammonia ambient.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: August 20, 2002
    Assignee: Applied Materials, Inc
    Inventors: Jianhua Hu, Yin Lin, Fufa Chen, Yehuda Demayo, Ming Xi
  • Publication number: 20020064952
    Abstract: The present invention is a semiconductor metallization process for providing complete via fill on a substrate and a planar metal surface, wherein the vias are free of voids and the metal surface is free of grooves. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A PVD metal layer, such as PVD Al or PVD Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr to provide a conformal PVD metal layer. Then the vias or contacts are filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably carried out in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by a long throw distance of at least 100 mm, and a hot metal PVD chamber that also serves as a reflow chamber.
    Type: Application
    Filed: December 21, 2001
    Publication date: May 30, 2002
    Inventors: Sang-Ho Yu, Yonghwa Chris Cha, Murali Abburi, Shri Singhvi, Fufa Chen
  • Patent number: 6364949
    Abstract: The present invention relates to plasma-enhanced chemical vapor deposition (PECVD) and related chamber hardware. Embodiments of the present invention include a PECVD system for depositing a film of titanium nitride from a TDMAT precursor. The present invention broadly provides a chamber, a gas delivery assembly, a pedestal which supports a substrate, and a plasma system to process substrates. In general, the invention includes a chamber body and a gas delivery assembly disposed thereon to define a chamber cavity. A pedestal movably disposed within the chamber cavity is adapted to support a substrate during processing. The gas delivery assembly is supported by the chamber body and includes a temperature control plate and a showerhead mounted thereto. Preferably, the interface between the showerhead and temperature control plate is parallel to a radial direction of the gas delivery assembly to accommodate lateral thermal expansion without separation of the showerhead and the temperature control plate.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: April 2, 2002
    Assignee: Applied Materials, Inc.
    Inventors: David T. Or, Keith K. Koai, Fufa Chen, Lawrence C. Lei
  • Patent number: 6352620
    Abstract: The present invention is a semiconductor metallization process for providing complete via fill on a substrate and a planar metal surface, wherein the vias are free of voids and the metal surface is free of grooves. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A PVD metal layer, such as PVD Al or PVD Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr to provide a conformal PVD metal layer. Then the vias or contacts are filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably carried out in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by a long throw distance of at least 100 mm, and a hot metal PVD chamber that also serves as a reflow chamber.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: March 5, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Sang-Ho Yu, Yonghwa Chris Cha, Murali Abburi, Shri Singhvi, Fufa Chen
  • Patent number: 6332601
    Abstract: The present invention provides for improved liquid vaporizer systems and methods for their use. Vaporizer systems of the present invention are likely to be particularly useful for the vaporization of liquids having a relatively low vapor pressure, such as TDMAT. In one preferred embodiment, a liquid vaporizer system (10) includes a vaporizer unit (16) having first and second inlets (50 and 60) and an outlet (62). The vaporizer system further includes a vessel (22) having an inlet (70) and an outlet (72), whereby the vessel inlet is operably connected to the vaporizer outlet. The vessel contains a plurality of passages (78) which operably connect the vessel inlet and the vessel outlet. In this manner, liquids and/or gases flowing into the vaporizer unit through either or both of its two inlets, exit the vaporizer unit outlet and enter the vessel inlet. Liquids and/or gases pass through the plurality of passages and exit the vessel outlet.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: December 25, 2001
    Assignee: Applied Materials
    Inventors: Joel M. Huston, Fufa Chen
  • Publication number: 20010047932
    Abstract: The present invention is a semiconductor metallization process for providing complete via fill on a substrate and a planar metal surface, wherein the vias are free of voids and the metal surface is free of grooves. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A PVD metal layer, such as PVD Al or PVD Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr to provide a conformal PVD metal layer. Then the vias or contacts are filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably carried out in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by a long throw distance of at least 100 mm, and a hot metal PVD chamber that also serves as a reflow chamber.
    Type: Application
    Filed: June 28, 1999
    Publication date: December 6, 2001
    Applicant: Applied Materials, Inc.
    Inventors: SANG-HO YU, YONGHWA CHRIS CHA, MURALI ABBURI, SHRI SINGHVI, FUFA CHEN
  • Patent number: 6220091
    Abstract: The present invention provides methods and systems for forming deposition films on semiconductor wafers. In particular, the present invention measures the amount of liquid remaining in a bubbler ampule of a semiconductor processing system used for chemical vapor deposition (CVD) on a semiconductor wafer. More particularly, measurements are made when gas has stopped flowing through the ampule, and the liquid is in a static condition. The system of the present invention comprises a container containing a liquid, a gas inlet for introduction of gas into the liquid, a gas outlet, and a pressure transducer fluidly connected to the gas inlet and the gas outlet. The device measures the amount of liquid in a bubbler ampule through measurements of gas pressure differential between gas exiting a nozzle near the bottom of the liquid and gas located above the level of the liquid. The depth of liquid remaining in the ampule may be extrapolated from the measured pressure differential.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: April 24, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Fufa Chen, Yu Chang, Gwo Tzu
  • Patent number: 6221174
    Abstract: The present invention is a method of wafer processing which improves the reliability of an integrated titanium (Ti)/titanium nitride (TiN) CVD film formed from a reaction of titanium tetrachloride (TiCi4) and ammonia (NH3). A Ti film is subject to a treatment of NH3 gas to render the Ti film unreactive towards attack by chlorine and hydrogen chloride. A thin seed layer of TiN film is deposited upon the treated Ti film using a thermal TiCl4/NH3 reaction. Subsequent TiN film deposition upon the seed layer results in a successful integration of a Ti/TiN film stack for a Ti film thickness up to about 300 Å.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: April 24, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Fufa Chen, Yin Lin, Jianhua Hu, Frederick Wu, Ming Xi, Li Wu
  • Patent number: 6179277
    Abstract: The present invention provides for improved liquid vaporizer systems and methods for their use. Vaporizer systems of the present invention are likely to be particularly useful for the vaporization of liquids having a relatively low vapor pressure, such as TDMAT. In one preferred embodiment, a liquid vaporizer system (10) includes a vaporizer unit (16) having first and second inlets (50 and 60) and an outlet (62). The vaporizer system further includes a vessel (22) having an inlet (70) and an outlet (72), whereby the vessel inlet is operably connected to the vaporizer outlet. The vessel contains a plurality of passages (78) which operably connect the vessel inlet and the vessel outlet. In this manner, liquids and/or gases flowing into the vaporizer unit through either or both of its two inlets, exit the vaporizer unit outlet and enter the vessel inlet. Liquids and/or gases pass through the plurality of passages and exit the vessel outlet.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: January 30, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Joel M. Huston, Fufa Chen
  • Patent number: 6086676
    Abstract: A vacuum processing system is provided with a programmable interlock circuit for combining the interlock signals generated by the system into combined interlock signals. The programmable interlock circuit uses a matrix of switches to select which interlocks will be combined to form which combinations. The interlock signals are formed by two lines that are shorted together when the interlock signal is okay and not shorted together when the interlock signal is not okay. When the two lines are shorted together, then they activate a relay to send a signal in a line of relays, each of which is activated by a different interlock signal. The matrix of switches short out the relay switches in order to deselect one interlock input for one interlock output. Each interlock signal is associated with an LED for visual indication of whether the interlock is okay. Likewise, each combined interlock signal is associated with an LED for visual indication of whether the combination of interlocks is okay.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: July 11, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Yeh-Jen Kao, Fufa Chen, James Chen