Patents by Inventor FUJITSU SEMICONDUCTOR LIMITED
FUJITSU SEMICONDUCTOR LIMITED has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140145692Abstract: A power supply device includes a coil, a first switch circuit that accumulates energy in the coil, and a plurality of second switch circuits that couple the coil to a plurality of output terminals. A first control unit generates a first control signal that controls the first switch circuit to turn on and off based on a combined value of a plurality of output voltages respectively output from the plurality of output terminals and a first reference value. A second control unit generates a second control signal that controls the plurality of second switch circuits to turn on and off in a cycle that is the same as the first control signal based on a first output voltage of the plurality of output voltages and a second reference value.Type: ApplicationFiled: April 9, 2013Publication date: May 29, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130224912Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.Type: ApplicationFiled: April 13, 2013Publication date: August 29, 2013Applicant: Fujitsu Semiconductor LimitedInventor: Fujitsu Semiconductor Limited
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Publication number: 20130223546Abstract: A local carrier wave output from a synthesizer to quadrature demodulators is multiplied by an offset that makes a frequency shift by an integer number of subcarriers in units of sub-carrier bands. The offset is set to a value obtained by multiplying the number sequentially counted up from 0 to the number of unused sub-carriers included in guard tones in a signal band by the bandwidth of a sub-carrier. By shifting the frequency of the local carrier wave at the time of quadrature demodulation with the offset, the SNR of a baseband signal is prevented from being constantly degraded by a frequency characteristic possessed by the circuit of a receiver in a particular sub-carrier signal. Especially, by preventing a pilot signal from being constantly degraded, the signal can be received with higher accuracy.Type: ApplicationFiled: April 10, 2013Publication date: August 29, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130222169Abstract: A digital-to-analog (D/A) converter includes D/A conversion circuits and an amplifier circuit coupled between the D/A conversion circuits. Each D/A conversion circuit includes an R-2R ladder type resistor network, first transistors coupled between the resistor network and a first wiring at a first voltage level, and second transistors coupled between the resistor network and a second wiring at a second voltage level. The sizes of the first transistors are set at a ratio of powers of 2. The sizes of second transistors are set at a ratio of powers of 2. The second transistors are respectively turned on and off complementarily to the first transistors according to the digital input signal.Type: ApplicationFiled: February 25, 2013Publication date: August 29, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130218576Abstract: An audio signal coding device divides a frequency spectrum obtained from an input digital signal to a plurality of bands, scales and quantizes divided frequency spectra based on a scalefactor of each of the bands and a common scale which is common to the plurality of bands, and codes quantized frequency spectra. The audio signal coding device includes a band number determination unit configured to calculate a number of coding bands for coding the quantized frequency spectra, and a common scale estimation unit configured to estimate the common scale in accordance with the number of coding bands.Type: ApplicationFiled: November 27, 2012Publication date: August 22, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130215700Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: ApplicationFiled: March 21, 2013Publication date: August 22, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130214957Abstract: An analog-to-digital conversion device has: an analog-to-digital converter configured to receive an input signal via an input signal node, and convert the input signal to a digital signal; and a control circuit configured to receive the digital signal when the input signal is set to have a fixed value, and change, when a deviation amount of the digital signal with the respect to an expected value is equal to or larger than a threshold value, a value of a capacitor between a power supply potential node and a reference potential node of the analog-to-digital converter and/or values of resistors connected to the power supply potential node and the reference potential node of the analog-to-digital converter.Type: ApplicationFiled: February 14, 2013Publication date: August 22, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130217194Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.Type: ApplicationFiled: February 7, 2013Publication date: August 22, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Fujitsu Semiconductor Limited
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Publication number: 20130215664Abstract: An activate signal generating circuit, to which a first and a second activate signals which are pulse signals are applied, and which generates an internal activate signal, has a first delay element. The internal activate signal is activated based on timings of front (active transient) edges of the first and second activate signals. When a timing of a rear (inactive transient) edge of the first activate signal is earlier than a timing of a rear edge of the second activate signal, the internal activate signal goes inactivate based on the timing of the rear edge of the first activate signal, and when the timing of the rear edge of the first activate signal is later than the timing of the rear edge of the second activate signal, the internal activate signal goes inactivate after a predetermined delay time based on a delay time of the first delay element.Type: ApplicationFiled: December 27, 2012Publication date: August 22, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130207193Abstract: A semiconductor device including a first insulation film including a first opening reaching a diffusion region of a transistor; a first barrier metal over the diffused region in the first opening; a first conduction layer formed over the first barrier metal in the first opening and formed of a first conductor; a second barrier metal formed over the first conduction layer in the first opening; a second conduction layer formed over the second barrier metal in the first opening and formed of a second conductor; a third barrier metal formed over the first gate electrode in the second opening; a fourth barrier metal formed in the second opening and contacting with the third barrier metal; and a third conduction layer formed of the second conductor contacting with the fourth barrier metal in the second opening.Type: ApplicationFiled: February 7, 2013Publication date: August 15, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130210169Abstract: A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.Type: ApplicationFiled: March 15, 2013Publication date: August 15, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130207625Abstract: A switching regulator controls an output transistor supplying current to an inductor and generates a second supply voltage from a first supply voltage. The switching regulator has: an error amplifier amplifying a difference between the second supply voltage and a reference voltage; a current sense amplifier converting an inductor current into voltage; a current comparator comparing an output voltages of the error amplifier and the current sense amplifier, so as to output a trigger signal when the second supply voltage decreases; a pulse generation circuit generating a control pulse to drive the first output transistor in response to the trigger signal; and a sleep control circuit, during a sleep period by a sleep signal supplied from a load side, suspending operation of the current sense amplifier or the pulse generation circuit, and tentatively resuming the suspended operation in response to the trigger signal, and thereafter suspending the operation again.Type: ApplicationFiled: December 3, 2012Publication date: August 15, 2013Applicant: Fujitsu Semiconductor LimitedInventor: Fujitsu Semiconductor Limited
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Publication number: 20130203186Abstract: Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example.Type: ApplicationFiled: March 14, 2013Publication date: August 8, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130200481Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.Type: ApplicationFiled: March 15, 2013Publication date: August 8, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130194025Abstract: A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.Type: ApplicationFiled: December 28, 2012Publication date: August 1, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130194125Abstract: A modulator that quantizes a first signal into a quantized signal having a plurality of bits includes an integrator performing sampling on the first signal in a first period, and to integrate a difference between the first signal and a reference signal in a second period; and a quantizer receiving a second signal which is an output of the integrator and operating in synchronization with a first clock having a cycle shorter than the first period, the quantizer generating the quantized signal on the basis of the second signal in the first period and outputting the reference signal on the basis of the quantized signal to the integrator.Type: ApplicationFiled: December 21, 2012Publication date: August 1, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130198526Abstract: A secure hardware comprises a secure pipe, a secure DMA, a secure assist and a secure bus, which connects between those blocks. The secure pipe stores a common encryption key in an encryption key table so as not to be able to access from software. The secure DMA comprises a data common key system process function and a hashing process function. The secure assist comprises a common key system process function and an authentication process function, receives an issued command from a program executed by the processor core via a public IF, and performs setting/control of the secure pipe and the secure DMA via the secure bus.Type: ApplicationFiled: March 8, 2013Publication date: August 1, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130193485Abstract: An embodiment of a compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; a two-dimensional electron gas suppressing layer formed over the electron supply layer; an insulating film formed over the two-dimensional electron gas suppressing layer and the electron transit layer; and a gate electrode formed over the insulating film. The gate electrode is electrically connected with the two-dimensional electron gas suppressing layer.Type: ApplicationFiled: December 31, 2012Publication date: August 1, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130196503Abstract: A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu.Type: ApplicationFiled: March 6, 2013Publication date: August 1, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED
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Publication number: 20130196482Abstract: A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen.Type: ApplicationFiled: November 30, 2012Publication date: August 1, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: FUJITSU SEMICONDUCTOR LIMITED