Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Abstract: A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.

Abstract: A first erase test is performed by applying an erase pulse to series of memory cells which are included in a memory cell array and which are divided into a plurality of groups until the appearance of a group for which the determination that erase is completed is made. A second erase test is performed on other series of memory cells including the series of memory cells on the basis of the number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.

Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.

Abstract: A disclosed method of manufacturing a semiconductor device includes forming a groove on a first surface of a semiconductor wafer along an outer periphery of the semiconductor wafer, forming a semiconductor device on the first surface, forming an adhesive layer on the first surface to cover the semiconductor device, bonding a support substrate to the first surface by the adhesive layer, grinding after the adhering of the support substrate a second surface of the semiconductor wafer opposite to the first surface, and dicing after the grinding the semiconductor wafer into individual semiconductor chips.

Abstract: In a semiconductor device, a first semiconductor element having a first terminal is embedded in a resin layer such that terminals thereof are exposed through a first surface of the resin layer. A wiring layer is formed in the first surface of the resin layer. A second semiconductor element includes second and third terminals. Regardless of the relationship between the plane size of the first semiconductor element and that of the second semiconductor element, the second terminal of the second semiconductor element is connected to the first terminal of the first semiconductor element exposed through the first surface of the resin layer, and the third terminal of the second semiconductor element is connected to the wiring layer formed in the resin layer.

Abstract: A power supply has first and second reference voltage sources; a step-down voltage generator, including a transistor supplied with a first voltage, a resistor string between the transistor and a second voltage, and an op-amp which controls the transistor, and outputting the voltage at a first node among nodes in the resistor string; switches, coupled to the nodes; a comparison circuit, which compares the voltage at a common node the switches coupling in common with the second reference voltage source; and a calibration control circuit, which selects any switch according to a comparison result to calibrate. During calibration, the calibration control circuit couples a second node among the nodes to a non-inverting terminal of the op-amp, and the first reference voltage source to an inverting terminal of the op-amp, and after calibration, couples the common node to the non-inverting terminal, and the second reference voltage source to the inverting terminal.

Abstract: A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO2 film) of a predetermined pattern is formed on the Pt film, and the Pt film and the upper electrode film are etched. Then, an insulating protective film is formed on an entire surface, and a side surface of the upper electrode film is covered with the insulating protective film. Next, the ferroelectric film and the lower electrode film are etched, thus forming a ferroelectric capacitor.

Abstract: A DC-DC converter includes a drive circuit configured to drive a first switching element, and a second switching element coupled between a low potential power terminal of the drive circuit and a first node corresponding to the input voltage or the output voltage. A current detecting section detects a load current flowing in the output terminal. A control circuit turns on a third switching element, which is coupled between the low potential power terminal of the drive circuit and a second node having a potential lower than both the input voltage and the output voltage, in a case where a difference between the input voltage and the output voltage is lower than a threshold. The control circuit controls the second and third switching elements based on a detection result of the current detecting section in a case where the difference is equal to or greater than the threshold.

Abstract: A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.

Abstract: A picture detection device includes an estimation unit configured to, based on deviations in color information of pixels of a prescribed number of lines in an upper-edge portion, lower-edge portion, left-edge portion, and right-edge portion of a picture frame including a first picture and a second picture displayed on the periphery of the first picture, estimate an edge portion of the picture frame in which the second picture is displayed from among above-described four portions; and a detection unit configured to detect the first picture of the picture flame; wherein the detection unit moves a borderline detection line from the center of the picture frame toward the estimated edge portion, and detects a borderline between the first picture and the second picture based on a brightness difference of pixels in the vicinity of the borderline detection line, and detects the first picture based on the detected borderline.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

Abstract: A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization.

Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass the a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter and is a frequency corresponding to the digital control signal.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.