Abstract: A drawing device includes a distinguish unit for distinguishing figure description information in scene data of each figure in a display screen, for tiles included in the display screen; an aggregation unit for aggregating a data size of the figure description information corresponding to the tiles; an address determination unit for determining a leading address in a memory area for storing the figure description information corresponding to each of the tiles, based on an aggregation result of each tile; and a memory write unit for sequentially writing, in the memory area, the figure description information distinguished as corresponding to the tiles, starting from the leading address determined for each corresponding tile, wherein the address determination unit determines the leading addresses so that the memory areas for storing the figure description information corresponding to the tiles are arranged in a physical address space in an order of drawing the tiles.

Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.

Abstract: A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer.

Abstract: In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate, and, at the same time, five isolation insulating films extending in one specific direction are formed within a monitor area at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate, and, at the same time, five gate insulation films and five gate electrodes extending in the same direction as the isolation insulating films are formed within the monitor area at the same spacing as that of the isolation insulating films.

Abstract: A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first interlayer insulating film over a substrate; forming a first conductive film over the first interlayer insulating film; forming a ferroelectric film on the first conductive film; forming a second conductive film on the ferroelectric film; forming an upper electrode of a capacitor by patterning the second conductive film; forming a capacitor dielectric film by patterning the ferroelectric film; and forming a lower electrode of the capacitor by patterning the first conductive film, wherein forming the first conductive film includes: forming a lower conductive layer made of a noble metal other than iridium over the first interlayer insulating film; and forming an upper conductive layer on the lower conductive layer, the upper conductive layer being made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.

Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.

Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.

Abstract: A semiconductor device includes a capacitor dielectric film formed on a lower electrode and made of a ferroelectric material, and an upper electrode formed on a capacitor dielectric film, wherein the lower electrode includes a lowest conductive layer and an upper conductive layer, the lowest conductive layer being made of a noble metal other than iridium, and the upper conductive layer being formed on the lowest conductive layer and made of a conductive material, which is different from a material for the lowest conductive layer, and which is other than platinum.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.

Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.