Abstract: A bonded assembly of a memory die and a logic die is provided. The memory die includes a memory array, a plurality of bit lines, and memory-side bit-line-connection bonding pads. The logic die includes sense amplifiers located in a sense amplifier region, and logic-side bit-line-connection bonding pads located within the sense amplifier region and bonded to a respective one of the memory-side bit-line-connection bonding pads. The sense amplifier region has an areal overlap with a respective first subset the plurality of bit lines in a plan view, while a second subset of the plurality of bit lines does not have an areal overlap with the sense amplifier region in the plan view.

Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

Abstract: A non-volatile memory includes a non-volatile memory array comprising blocks of non-volatile memory cells, bit lines connected to the memory cells and word lines connected to the memory cells. Word line switch transistors connect the word lines to voltage sources. The word line switch transistors are positioned in triple wells. Multiple triple wells are utilized and the word line switch transistors are grouped into triple wells based on word line voltage ranges used during the programming process. In one embodiment, for a given block, the word line switch transistors connected to data word lines are positioned in a first triple well and the word line switch transistors connected to selection and dummy word lines are positioned in a second triple well. This structure allows the triple wells to be biased differently.

Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, where each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, drain regions contacting an upper end of a respective one of the vertical semiconductor channels, first contact via structures directly contacting a first subset of the drain regions and each having a first horizontal cross-sectional area, and second contact via structures directly contacting a second subset of the drain regions and each having a second horizontal cross-sectional area that is greater than the first horizontal cross-sectional area.

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.

Abstract: A first vertically alternating sequence of first insulating layers and first spacer material layers and a first-tier retro-stepped dielectric material portion are formed over a substrate. The first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers. A second vertically alternating sequence of second insulating layers and second spacer material layers and a second-tier retro-stepped dielectric material portion are formed over the first vertically alternating sequence and the first-tier retro-stepped dielectric material portion. The second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers. An opening is formed through the second vertically alternating sequence over the first-tier retro-stepped dielectric material portion, and is filled with a dielectric well structure.

Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.

Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.