Patents by Inventor Fumio Murai

Fumio Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080057408
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: March 16, 2005
    Publication date: March 6, 2008
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 7115344
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: October 3, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 6964832
    Abstract: A method is provided for solving a problem that the fine processing property is degraded by an increase of a current applied to complementarily divided masks in an electron beam projection process. In the method, the complementarily divided masks used for electron projection are used whereby one mask is used for patterns requiring high dimensional accuracy and another is used for other patterns. Consequently, it is possible to lower the current applied to the patterns requiring high dimensional accuracy to realize high printing accuracy. In addition, the highly accurate patterns can be formed at a high throughput.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: November 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Akemi Moniwa, Jiro Yamamoto, Fumio Murai, Hiroshi Fukuda
  • Publication number: 20050158638
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: March 16, 2005
    Publication date: July 21, 2005
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 6845497
    Abstract: Patterns for exposure are divided into subdivided regions taking into consideration a scope of an effect of backscattering, the Coulomb effect, and process factors, respectively, on errors in dimensions, and a pattern area occupancy ratio (pattern area density) within the respective subdivided regions is retained, thereby executing exposure with patterns after finding dimensions of pattern modification as the function of the respective pattern area densities. As a result, it becomes possible to fabricate a mask provided with correction for the errors in the dimensions, caused by plural factors such as backscattering, the Coulomb effect, and process factors, and to obtain highly accurate patterns for exposure. Further, use of pattern area density maps enables data processing time necessary for correction to be considerably reduced.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: January 18, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Murai, Hiroshi Fukuda
  • Publication number: 20040161707
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 19, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 6733953
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: May 11, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 6709880
    Abstract: There is disclosed a method for forming micro patterns in a semiconductor integrated circuit device with high productivity and high accuracy. A photolithography having high throughput and electron beam lithography using a reticle and having relatively high throughput and high resolution are selectively used so as to obtain highest throughput while satisfying accuracy and resolution required for each product/layer. In the case of using the electron beam lithography, a non-complementary reticle and a complementary reticle are selectively used so as to obtain highest throughput while satisfying required accuracy and resolution. Thus, productivity and integration can be improved for the semiconductor integrated circuit device.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: March 23, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems, Co., Ltd.
    Inventors: Jiro Yamamoto, Fumio Murai, Tsuneo Terasawa, Tosiyuki Yamamoto
  • Publication number: 20030228758
    Abstract: Disclosed herewith is a method for solving a conventional problem that the fine processing property is degraded by an increase of a current applied to complementarily divided masks in an electron beam projection process.
    Type: Application
    Filed: February 27, 2003
    Publication date: December 11, 2003
    Inventors: Akemi Moniwa, Jiro Yamamoto, Fumio Murai, Hiroshi Fukuda
  • Patent number: 6586341
    Abstract: To provide a method of manufacturing a semiconductor device for manufacturing a minute pattern with high accuracy using a stencil mask. An input layout data is classified into rectangles according to pattern width or the like, a boundary is created that divides a periphery or an inside of each classified graphics, an input pattern is fractionized by the boundary, and a complementary mask with fractionized patterns on both sides of the boundary distributed into different layers is used to form a pattern.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: July 1, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Akemi Moniwa, Hiroshi Fukuda, Fumio Murai
  • Publication number: 20030093767
    Abstract: Patterns for exposure are divided into subdivided regions taking into consideration a scope of an effect of backscattering, the Coulomb effect, and process factors, respectively, on errors in dimensions, and a pattern area occupancy ratio (pattern area density) within the respective subdivided regions is retained, thereby executing exposure with patterns after finding dimensions of pattern modification as the function of the respective pattern area densities. As a result, it becomes possible to fabricate a mask provided with correction for the errors in the dimensions, caused by plural factors such as backscattering, the Coulomb effect, and process factors, and to obtain highly accurate patterns for exposure. Further, use of pattern area density maps enables data processing time necessary for correction to be considerably reduced.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 15, 2003
    Inventors: Fumio Murai, Hiroshi Fukuda
  • Publication number: 20030054580
    Abstract: There is disclosed a method for forming micro patterns in a semiconductor integrated circuit device with high productivity and high accuracy. A photolithography having high throughput and electron beam lithography using a reticle and having relatively high throughput and high resolution are selectively used so as to obtain highest throughput while satisfying accuracy and resolution required for each product/layer. In the case of using the electron beam lithography, a non-complementary reticle and a complementary reticle are selectively used so as to obtain highest throughput while satisfying required accuracy and resolution. Thus, productivity and integration can be improved for the semiconductor integrated circuit device.
    Type: Application
    Filed: June 17, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Jiro Yamamoto, Fumio Murai, Tsuneo Terasawa, Tosiyuki Yamamoto
  • Patent number: 6518548
    Abstract: So as to provide a substrate temperature control system capable of unifying the temperature of the substrate and capable of shortening the temperature elevation time (temperature lowering time), the substrate temperature control system is equipped with a temperature control plate (heating or cooling plate) having a plurality of projections on the surface and serving to set the temperature of the substrate, and a chuck mechanism to fix the substrate in contact to a plurality of the projections by chucking the substrate toward the direction of the temperature control plate.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: February 11, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Sugaya, Fumio Murai, Yutaka Kaneko, Masafumi Kanetomo, Shigeki Hirasawa, Tomoji Watanabe, Tatuharu Yamamoto, Katsuhiro Kuroda
  • Patent number: 6497992
    Abstract: In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: December 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Yunogami, Shunji Sasabe, Kazuyuki Suko, Jun Abe, Takao Kumihashi, Fumio Murai
  • Publication number: 20020175298
    Abstract: To provide a method of manufacturing a semiconductor device for manufacturing a minute pattern with high accuracy using a stencil mask. An input layout data is classified into rectangles according to pattern width or the like, a boundary is created that divides a periphery or an inside of each classified graphics, an input pattern is fractionized by the boundary, and a complementary mask with fractionized patterns on both sides of the boundary distributed into different layers is used to form a pattern.
    Type: Application
    Filed: February 27, 2002
    Publication date: November 28, 2002
    Inventors: Akemi Moniwa, Hiroshi Fukuda, Fumio Murai
  • Publication number: 20020113056
    Abstract: So as to provide a substrate temperature control system capable of unifying the temperature of the substrate and capable of shortening the temperature elevation time (temperature lowering time), the substrate temperature control system is equipped with a temperature control plate (heating or cooling plate) having a plurality of projections on the surface and serving to set the temperature of the substrate, and a chuck mechanism to fix the substrate in contact to a plurality of the projections by chucking the substrate toward the direction of the temperature control plate.
    Type: Application
    Filed: February 28, 2002
    Publication date: August 22, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Masakazu Sugaya, Fumio Murai, Yutaka Kaneko, Masafumi Kanetomo, Shigeki Hirasawa, Tomoji Watanabe, Tatuharu Yamamoto, Katsuhiro Kuroda
  • Publication number: 20020102478
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: March 14, 2002
    Publication date: August 1, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Patent number: 6394797
    Abstract: To provide a substrate temperature control system capable of unifying the temperature of the substrate and capable of shortening the temperature elevation time (temperature lowering time), the substrate temperature control system is equipped with a temperature control plate (heating or cooling plate) having a plurality of projections on its surface and acting to set the temperature of the substrate. A chuck mechanism is provided to fix the substrate in contact with a plurality of the projections by chucking the substrate toward the temperature control plate.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: May 28, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Sugaya, Fumio Murai, Yutaka Kaneko, Masafumi Kanetomo, Shigeki Hirasawa, Tomoji Watanabe, Tatuharu Yamamoto, Katsuhiro Kuroda
  • Patent number: 6383718
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: May 7, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano
  • Publication number: 20010036583
    Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
    Type: Application
    Filed: June 29, 2001
    Publication date: November 1, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Norio Hasegawa, Fumio Murai, Katsuya Hayano