Patents by Inventor Fumitaka Amano

Fumitaka Amano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170373079
    Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.
    Type: Application
    Filed: April 10, 2017
    Publication date: December 28, 2017
    Inventors: Rahul SHARANGPANI, Fumitaka AMANO, Raghuveer S. MAKALA, Fei ZHOU, Keerti SHUKLA
  • Publication number: 20170247794
    Abstract: A process chamber includes multiple partitions within a single continuous vacuum enclosure. Each of the multiple partitions is defined by respective distinct volumes within the single continuous vacuum enclosure that are connected thereamongst for unhindered movement of a substrate therethrough. The multiple partitions are configured to provide different process gases or purge gases to the substrate as the substrate cycles through the multiple positions. The process can cycle through a first deposition step that deposits a first material on the substrate in a first position and a second deposition step that deposits a second material on the substrate in a second position within each cycle. Alternatively or additionally, the process spaces can include at least one precursor treatment space and at least one reaction space.
    Type: Application
    Filed: July 26, 2016
    Publication date: August 31, 2017
    Inventors: Yusuke MUKAE, Fumitaka AMANO, Naoki TAKEGUCHI
  • Patent number: 9748174
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are removed to form backside recesses. The backside recesses are sequentially filled with a continuous layer stack including a first continuous metallic nitride layer, a continuous tungsten layer, a second continuous metallic nitride layer, and a continuous metal fill layer. The continuous layer stack is patterned to form electrically conductive layers. Each electrically conductive layer includes a liner stack of a first metallic nitride liner, a tungsten liner, and a second metallic nitride liner. The liner stack is a diffusion barrier for high diffusivity species such as fluorine and boron.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: August 29, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Fumitaka Amano
  • Patent number: 9607888
    Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
  • Patent number: 9558962
    Abstract: A method for passivating a surface of a semiconductor substrate with fluorine-based layer to protect the surface against oxidation and allow longer queue times. According to one embodiment, the method includes providing a substrate having an oxidized layer formed thereon, replacing the oxidized layer with a fluorine-based layer, exposing the fluorine-based layer to an oxidizing atmosphere, where the fluorine-based layer protects the substrate against oxidation by the oxidizing atmosphere, and removing the fluorine-based layer from the substrate using a plasma process.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: January 31, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Fumitaka Amano
  • Publication number: 20160049309
    Abstract: A method for passivating a surface of a semiconductor substrate with fluorine-based layer to protect the surface against oxidation and allow longer queue times. According to one embodiment, the method includes providing a substrate having an oxidized layer formed thereon, replacing the oxidized layer with a fluorine-based layer, exposing the fluorine-based layer to an oxidizing atmosphere, where the fluorine-based layer protects the substrate against oxidation by the oxidizing atmosphere, and removing the fluorine-based layer from the substrate using a plasma process.
    Type: Application
    Filed: August 11, 2015
    Publication date: February 18, 2016
    Inventors: Kandabara N. Tapily, Fumitaka Amano
  • Publication number: 20150221550
    Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.
    Type: Application
    Filed: February 3, 2015
    Publication date: August 6, 2015
    Inventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
  • Patent number: 7981794
    Abstract: A barrier layer including a titanium film is formed at a low temperature, and a TiSix film is self-conformably formed at the interface between the titanium film and the base. In forming the TiSix film 507, the following steps are repeated without introducing argon gas: a first step of introducing a titanium compound gas into the processing chamber to adsorb the titanium compound gas onto the silicon surface of a silicon substrate 502; a second step of stopping introduction of the titanium compound gas into the processing chamber and removing the titanium compound gas remaining in the processing chamber; and a third step of generating plasma in the processing chamber while introducing hydrogen gas into the processing chamber to reduce the titanium compound gas adsorbed on the silicon surface and react it with the silicon in the silicon surface to form the TiSix film 507.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: July 19, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kensaku Narushima, Fumitaka Amano, Satoshi Wakabayashi
  • Publication number: 20100304561
    Abstract: A barrier layer including a titanium film is formed at a low temperature, and a TiSix film is self-conformably formed at the interface between the titanium film and the base. In forming the TiSix film 507, the following steps are repeated without introducing argon gas: a first step of introducing a titanium compound gas into the processing chamber to adsorb the titanium compound gas onto the silicon surface of a silicon substrate 502; a second step of stopping introduction of the titanium compound gas into the processing chamber and removing the titanium compound gas remaining in the processing chamber; and a third step of generating plasma in the processing chamber while introducing hydrogen gas into the processing chamber to reduce the titanium compound gas adsorbed on the silicon surface and react it with the silicon in the silicon surface to form the TiSix film 507.
    Type: Application
    Filed: August 7, 2007
    Publication date: December 2, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kensaku Narushima, Fumitaka Amano, Satoshi Wakabayashi