Patents by Inventor Fumitaka Arai

Fumitaka Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018148
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Watanabe, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Wataru Sakamoto, Tatsuya Kato
  • Patent number: 11011541
    Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 18, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke Nakatsuka, Fumitaka Arai
  • Patent number: 10991713
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Keisuke Nakatsuka, Fumitaka Arai, Shinya Arai, Yasuhiro Uchiyama
  • Publication number: 20210013229
    Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 14, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Haruka SAKUMA, Hidenori MIYAGAWA, Shosuke FUJI, Kiwamu SAKUMA, Fumitaka ARAI, Kunifumi SUZUKI
  • Patent number: 10879261
    Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Fumitaka Arai
  • Patent number: 10868037
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Masakazu Goto, Masaki Kondo, Keiji Hosotani, Nobuyuki Momo
  • Publication number: 20200357810
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru SAKAMOTO, Ryota SUZUKI, Tatsuya OKAMOTO, Tatsuya KATO, Fumitaka ARAI
  • Patent number: 10833103
    Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Haruka Sakuma, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai
  • Publication number: 20200303400
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.
    Type: Application
    Filed: July 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka ARAI, Masakazu GOTO, Masaki KONDO, Keiji HOSOTANI, Nobuyuki MOMO
  • Publication number: 20200303403
    Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke NAKATSUKA, Fumitaka ARAI
  • Publication number: 20200303418
    Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Haruka SAKUMA, Hidenori Miyagawa, Shosuke Fujii, Kiwamu Sakuma, Fumitaka Arai
  • Publication number: 20200286828
    Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 10, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Fumitaka ARAI, Keisuke NAKATSUKA, Nobuyuki MOMO, Motohiko FUJIMATSU
  • Patent number: 10763272
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
  • Patent number: 10686045
    Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto
  • Publication number: 20200176033
    Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.
    Type: Application
    Filed: September 5, 2019
    Publication date: June 4, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Fumitaka ARAI, Keisuke NAKATSUKA
  • Patent number: 10650900
    Abstract: A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shimada, Fumitaka Arai, Tatsuya Kato
  • Patent number: 10650894
    Abstract: A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer pr
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kato, Yusuke Shimada, Fumitaka Arai
  • Publication number: 20200135242
    Abstract: According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer.
    Type: Application
    Filed: July 3, 2019
    Publication date: April 30, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka ARAI, Keiji HOSOTANI, Nobuyuki MOMO
  • Patent number: 10636803
    Abstract: A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Kohei Sakaike, Satoshi Nagashima
  • Publication number: 20200098784
    Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.
    Type: Application
    Filed: March 8, 2019
    Publication date: March 26, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi NAGASHIMA, Fumitaka ARAI