Patents by Inventor Fumiya Watanabe
Fumiya Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097658Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.Type: ApplicationFiled: March 3, 2023Publication date: March 21, 2024Inventors: Fumiya WATANABE, Toshifumi WATANABE, Kazuhiko SATOU, Shouichi OZAKI, Kenro KUBOTA, Atsuko SAEKI, Ryota TSUCHIYA, Harumi ABE
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Publication number: 20240079067Abstract: A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.Type: ApplicationFiled: February 28, 2023Publication date: March 7, 2024Inventors: Shouichi OZAKI, Kazuhiko SATOU, Kenro KUBOTA, Fumiya WATANABE, Atsuko SAEKI, Ryota TSUCHIYA, Harumi ABE, Toshifumi WATANABE
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Patent number: 11450390Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.Type: GrantFiled: December 11, 2020Date of Patent: September 20, 2022Assignee: Kioxia CorporationInventors: Fumiya Watanabe, Masaru Koyanagi, Yutaka Shimizu, Yasuhiro Hirashima, Kei Shiraishi, Mikihiko Ito
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Patent number: 11211130Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: GrantFiled: May 5, 2020Date of Patent: December 28, 2021Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
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Patent number: 11177008Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.Type: GrantFiled: June 8, 2020Date of Patent: November 16, 2021Assignee: KIOXIA CORPORATIONInventors: Kensuke Yamamoto, Fumiya Watanabe, Shouichi Ozaki
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Publication number: 20210295930Abstract: According to one embodiment, in a semiconductor integrated circuit, an input circuit has an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit and a second time constant adjusting circuit. The first transistor has a gate that receives an input signal. The second transistor has a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.Type: ApplicationFiled: December 11, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Fumiya WATANABE, Masaru KOYANAGI, Yutaka SHIMIZU, Yasuhiro HIRASHIMA, Kei SHIRAISHI, Mikihiko ITO
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Patent number: 10914958Abstract: A vehicle display device includes an HUD device that projects a display image onto a front windshield arranged in front of a driver's seat of a vehicle, and overlaps the display image with scenery in front of the vehicle to display the display image as a virtual image, and a front photographing camera that is installed in the vehicle and photographs at least the scenery in front of the vehicle. The HUD device adjusts contrast of the display image with respect to the scenery in front of the vehicle based on an image of an extracted image region including a portion overlapping with at least part of the display image when viewed from an eye point in a scenery photographing image photographed by the front photographing camera, the eye point corresponding to a position of an eye of a driver on the driver's seat.Type: GrantFiled: October 23, 2017Date of Patent: February 9, 2021Assignee: YAZAKI CORPORATIONInventor: Fumiya Watanabe
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Patent number: 10916276Abstract: According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.Type: GrantFiled: February 20, 2019Date of Patent: February 9, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensuke Yamamoto, Kosuke Yanagidaira, Fumiya Watanabe, Shouichi Ozaki
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Patent number: 10847232Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: GrantFiled: August 29, 2019Date of Patent: November 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
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Publication number: 20200303021Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Kensuke YAMAMOTO, Fumiya WATANABE, Shouichi OZAKI
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Publication number: 20200265902Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Patent number: 10720221Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.Type: GrantFiled: September 2, 2018Date of Patent: July 21, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensuke Yamamoto, Fumiya Watanabe, Shouichi Ozaki
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Publication number: 20200202959Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: ApplicationFiled: August 29, 2019Publication date: June 25, 2020Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yumi TAKADA, Yasuhiro HIRASHIMA, Satoshi INOUE, Kensuke YAMAMOTO, Shouichi OZAKI, Taichi WAKUI, Fumiya WATANABE
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Patent number: 10679710Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: GrantFiled: September 2, 2018Date of Patent: June 9, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
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Publication number: 20200089630Abstract: According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.Type: ApplicationFiled: February 20, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kensuke YAMAMOTO, Kosuke YANAGIDAIRA, Fumiya WATANABE, Shouichi OZAKI
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Publication number: 20190295661Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: ApplicationFiled: September 2, 2018Publication date: September 26, 2019Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Publication number: 20190228826Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.Type: ApplicationFiled: September 2, 2018Publication date: July 25, 2019Inventors: Kensuke YAMAMOTO, Fumiya WATANABE, Shouichi OZAKI
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Publication number: 20180120572Abstract: A vehicle display device includes an HUD device that projects a display image onto a front windshield arranged in front of a driver's seat of a vehicle, and overlaps the display image with scenery in front of the vehicle to display the display image as a virtual image, and a front photographing camera that is installed in the vehicle and photographs at least the scenery in front of the vehicle. The HUD device adjusts contrast of the display image with respect to the scenery in front of the vehicle based on an image of an extracted image region including a portion overlapping with at least part of the display image when viewed from an eye point in a scenery photographing image photographed by the front photographing camera, the eye point corresponding to a position of an eye of a driver on the driver's seat.Type: ApplicationFiled: October 23, 2017Publication date: May 3, 2018Inventor: Fumiya Watanabe
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Patent number: 9634629Abstract: According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second P-type transistors; a second amplifier circuit including first and second N-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second P-type transistors. The third and fourth current mirror circuits are connected to drains of the first and second N-type transistors. The sixth current mirror circuit is connected to the first, fourth and fifth current mirror circuits. The seventh current mirror circuit is connected to the second, third and fifth current mirror circuits.Type: GrantFiled: October 28, 2014Date of Patent: April 25, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Fumiya Watanabe, Mikihiko Ito, Masaru Koyanagi
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Patent number: 9571101Abstract: According to one embodiment, a semiconductor device includes: a first circuit including a first transistor, a second transistor, the first and second transistors being capable of receiving first and second signals, respectively; a second circuit including a third transistor and a fourth transistor, a gate and one end of the third transistor being connected to one end of the first transistor, the fourth transistor being capable of receiving the first signal, one end of the fourth transistor being connected to the other end of the third transistor; and a third circuit configured to charge or discharge a node being connected to the one end of the first transistor according to the first signal.Type: GrantFiled: September 4, 2015Date of Patent: February 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Fumiya Watanabe, Mikihiko Ito, Masaru Koyanagi