Patents by Inventor Futoshi Hosoya

Futoshi Hosoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10243492
    Abstract: A semiconductor device includes a pulse generation circuit which generates a pulse control signal for selectively supplying currents to the coils with the coil phases of the brushless DC motor, a selector circuit which selects arbitrary two signals, from detection signals corresponding to currents flowing respectively to the coils and a reference signal, a comparator circuit which compares the two signals selected by the selector circuit, timer counter, and a control circuit. The control circuit repeatedly controls an operation for the pulse generation circuit to output a pulse control signal for supplying electricity to one of the coil phases in a state where the rotor is stopped, an operation for the selector circuit selects the reference signal and one of the detection signals, from the detection signals.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsuko Maekawa, Yuuki Akashi, Tetsuhiko Inoue, Futoshi Hosoya
  • Publication number: 20190006969
    Abstract: A semiconductor device includes a pulse generation circuit which generates a pulse control signal for selectively supplying currents to the coils with the coil phases of the brushless DC motor, a selector circuit which selects arbitrary two signals, from detection signals corresponding to currents flowing respectively to the coils and a reference signal, a comparator circuit which compares the two signals selected by the selector circuit, timer counter, and a control circuit. The control circuit repeatedly controls an operation for the pulse generation circuit to output a pulse control signal for supplying electricity to one of the coil phases in a state where the rotor is stopped, an operation for the selector circuit selects the reference signal and one of the detection signals, from the detection signals.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 3, 2019
    Inventors: Atsuko MAEKAWA, Yuuki Akashi, Tetsuhiko Inoue, Futoshi Hosoya
  • Patent number: 10075111
    Abstract: When electricity is supplied sequentially one by one to coils with a plurality of coil phases provided in a stator of a brushless DC motor, detection is made on a difference of signals corresponding to currents flowing respectively to coils with another plurality of coil phases coupled to the electrically conductive coil phases due to an effect of a magnetic flux of a stopped rotor. A stop position of the rotor with respect to the stator is determined, based on the relationship between a result of the detection operation and a coil phase in association with each other.
    Type: Grant
    Filed: July 11, 2015
    Date of Patent: September 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsuko Maekawa, Yuuki Akashi, Tetsuhiko Inoue, Futoshi Hosoya
  • Publication number: 20160094168
    Abstract: When electricity is supplied sequentially one by one to coils with a plurality of coil phases provided in a stator of a brushless DC motor, detection is made on a difference of signals corresponding to currents flowing respectively to coils with another plurality of coil phases coupled to the electrically conductive coil phases due to an effect of a magnetic flux of a stopped rotor. A stop position of the rotor with respect to the stator is determined, based on the relationship between a result of the detection operation and a coil phase in association with each other.
    Type: Application
    Filed: July 11, 2015
    Publication date: March 31, 2016
    Inventors: Atsuko MAEKAWA, Yuuki AKASHI, Tetsuhiko INOUE, Futoshi HOSOYA
  • Publication number: 20070210440
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 13, 2007
    Applicant: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 7242085
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: July 10, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 7145230
    Abstract: The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 5, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Publication number: 20050161802
    Abstract: The present invention provides a semiconductor device which comprises a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 28, 2005
    Applicant: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 6882040
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: April 19, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 6879033
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: April 12, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Publication number: 20050040503
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Application
    Filed: September 22, 2004
    Publication date: February 24, 2005
    Applicant: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 6853066
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: February 8, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Publication number: 20040201034
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Application
    Filed: April 28, 2004
    Publication date: October 14, 2004
    Inventor: Futoshi Hosoya
  • Publication number: 20040201092
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Application
    Filed: April 28, 2004
    Publication date: October 14, 2004
    Inventor: Futoshi Hosoya
  • Publication number: 20040021216
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Application
    Filed: July 3, 2003
    Publication date: February 5, 2004
    Inventor: Futoshi Hosoya
  • Patent number: 6072122
    Abstract: In a method for manufacturing an electronic apparatus, an electronic component is mounted on an organic substrate within its cavity. The electronic component is sealed by a concave molded resin enveloper filled into the cavity.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: June 6, 2000
    Assignee: NEC Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 5795799
    Abstract: In a method for manufacturing an electronic apparatus, an electronic component is mounted on an organic substrate within its cavity. The electronic component is sealed by a concave molded resin enveloper filled into the cavity.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: August 18, 1998
    Assignee: NEC Corporation
    Inventor: Futoshi Hosoya