Patents by Inventor Gabriel Banarie
Gabriel Banarie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10236905Abstract: Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.Type: GrantFiled: February 21, 2018Date of Patent: March 19, 2019Assignee: Analog Devices Global Unlimited CompanyInventors: Andreas Callanan, Adrian Sherry, Gabriel Banarie, Colin G. Lyden
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Patent number: 9806552Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.Type: GrantFiled: June 1, 2016Date of Patent: October 31, 2017Assignee: Analog Devices GlobalInventors: Paraic Brannick, Colin G. Lyden, Damien J. McCartney, Gabriel Banarie
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Patent number: 9800262Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.Type: GrantFiled: September 7, 2016Date of Patent: October 24, 2017Assignee: Analog Devices GlobalInventors: Roberto Sergio Matteo Maurino, Sanjay Rajasekhar, Pasquale Delizia, Colin G. Lyden, Gabriel Banarie
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Publication number: 20170255221Abstract: The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.Type: ApplicationFiled: March 20, 2017Publication date: September 7, 2017Inventors: Stefan Marinca, Gabriel Banarie
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Publication number: 20170237268Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.Type: ApplicationFiled: June 1, 2016Publication date: August 17, 2017Inventors: Paraic Brannick, Colin G. Lyden, Damien J. McCartney, Gabriel Banarie
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Patent number: 9600014Abstract: The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.Type: GrantFiled: May 7, 2014Date of Patent: March 21, 2017Assignee: Analog Devices GlobalInventors: Stefan Marinca, Gabriel Banarie
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Patent number: 9389275Abstract: Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.Type: GrantFiled: January 31, 2012Date of Patent: July 12, 2016Assignee: Analog Devices, Inc.Inventors: Gabriel Banarie, Andreas Callanan, Damien McCartney, Colin Lyden
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Publication number: 20150323950Abstract: The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.Type: ApplicationFiled: May 7, 2014Publication date: November 12, 2015Applicant: ANALOG DEVICES TECHNOLOGYInventors: Stefan MARINCA, Gabriel BANARIE
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Patent number: 9124290Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.Type: GrantFiled: February 1, 2013Date of Patent: September 1, 2015Assignee: ANALOG DEVICES GLOBALInventors: Adrian W. Sherry, Gabriel Banarie, Roberto S. Maurino
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Patent number: 8653996Abstract: A sigma-delta analog-to-digital converter (“?? ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ?? ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ?? ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.Type: GrantFiled: November 26, 2012Date of Patent: February 18, 2014Assignee: Analog Devices, Inc.Inventors: Gabriel Banarie, Adrian Sherry
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Publication number: 20130207821Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. Configurations are disclosed for analog and digital input signals.Type: ApplicationFiled: February 1, 2013Publication date: August 15, 2013Applicant: Analog Devices TechnologyInventors: Adrian W. SHERRY, Gabriel BANARIE, Roberto S. MAURINO
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Publication number: 20130207819Abstract: A sigma-delta analog-to-digital converter (“?? ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ?? ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ?? ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.Type: ApplicationFiled: November 26, 2012Publication date: August 15, 2013Inventors: Gabriel BANARIE, Adrian SHERRY
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Publication number: 20130193982Abstract: Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: ANALOG DEVICES, INC.Inventors: Gabriel Banarie, Andreas Callanan, Damien McCartney, Colin Lyden
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Patent number: 7304483Abstract: A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said secoType: GrantFiled: June 25, 2007Date of Patent: December 4, 2007Assignee: Analog Devices, Inc.Inventors: John O'Dowd, Damien McCartney, Gabriel Banarie
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Publication number: 20070247171Abstract: A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said secoType: ApplicationFiled: June 25, 2007Publication date: October 25, 2007Inventors: John O'Dowd, Damien McCartney, Gabriel Banarie
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Patent number: 7235983Abstract: A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined firstType: GrantFiled: March 8, 2006Date of Patent: June 26, 2007Assignee: Analog Devices, Inc.Inventors: John O'Dowd, Damien McCartney, Gabriel Banarie
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Publication number: 20060213270Abstract: A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined firstType: ApplicationFiled: March 8, 2006Publication date: September 28, 2006Inventors: John O'Dowd, Damien McCartney, Gabriel Banarie