Patents by Inventor Gabriel C. Risk

Gabriel C. Risk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8395389
    Abstract: A generator generates electricity by non-combustion means. A battery stores the generated electricity. An electrical appliance is powered by the stored electricity. A metering device tallies an operating parameter indicative of the amount of electrical energy consumed by the appliance. A housing supports the generator, the battery, the appliance and the metering device. A device, including the generator, the battery, the metering device and the housing, is manually portable.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: March 12, 2013
    Assignee: D. Light Design, Inc.
    Inventors: Nedjip Orhan Tozun, Gabriel C. Risk, Samuel W. Goldman, Xianyi Wu, Erica D. Estrada
  • Patent number: 8249199
    Abstract: A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 21, 2012
    Assignee: Oracle America, Inc.
    Inventors: Drew G. Doblar, Dawei Huang, Gabriel C. Risk
  • Patent number: 8229048
    Abstract: A method, apparatus, and system for minimizing ringing in a high speed channel between a transmitter and a receiver in a circuit, including a component for initializing an n-tap equalization filter. The n-tap equalization filter includes numerous taps, each associated with each of numerous jitter pulses received from the transmitter at the receiver and over the channel. Many of the jitter pulses are greater than two. Further, each tap occurs at a time-domain point related to a time of a corresponding jitter pulse included within the numerous jitter pulses. Moreover, a component for applying the n-tap equalization filter to a subsequent signal sent over the channel is also included.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: July 24, 2012
    Assignee: Oracle America, Inc.
    Inventors: Gabriel C. Risk, Drew G. Doblar, Pruthvi A. Chaudhari
  • Publication number: 20110148422
    Abstract: A generator generates electricity by non-combustion means. A battery stores the generated electricity. An electrical appliance is powered by the stored electricity. A metering device tallies an operating parameter indicative of the amount of electrical energy consumed by the appliance. A housing supports the generator, the battery, the appliance and the metering device. A device, including the generator, the battery, the metering device and the housing, is manually portable.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Inventors: Nedjip Orhan Tozun, Gabriel C. Risk, Samuel W. Goldman, Xianyi Wu, Erica D. Estrada
  • Patent number: 7898261
    Abstract: A lamp includes a generator that generates electricity. A battery stores the generated electricity. A light source produces light from the stored electricity. A metering device tallies an operating parameter indicative of the amount of electrical energy consumed by the lamp.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: March 1, 2011
    Assignee: D.Light Design, Inc.
    Inventors: Nedjip Orhan Tozun, Gabriel C. Risk, Samuel W. Goldman, Xianyi Wu, Erica D. Estrada
  • Publication number: 20100158177
    Abstract: A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Drew G. Doblar, Dawei Huang, Gabriel C. Risk
  • Patent number: 7636408
    Abstract: An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: December 22, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Jason H. Bau, Drew G. Doblar, Gabriel C. Risk
  • Publication number: 20090284261
    Abstract: A lamp includes a generator that generates electricity. A battery stores the generated electricity. A light source produces light from the stored electricity. A metering device tallies an operating parameter indicative of the amount of electrical energy consumed by the lamp.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Inventors: Nedjip Orhan Tozun, Gabriel C. Risk, Samuel W. Goldman, Xianyi Wu, Erica D. Estrada
  • Patent number: 7555085
    Abstract: A data receiver system. The system includes a clock generator configured to output a reference clock and circuitry configured to measure a direction of a phase difference between an input data stream and the reference clock. The circuitry is further configured to increment a counter if the phase difference is in a first direction, decrement the counter if the phase difference is in a direction opposite to the first direction, and convey a phase correction signal to the clock generator if an output value of the counter meets or exceeds a threshold. The clock generator is configured to adjust the phase of the reference clock in response to receiving the phase correction signal.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: June 30, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Gabriel C. Risk, Naveen G. Malur, Jason H. Bau
  • Patent number: 7533212
    Abstract: A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a switching circuit within a memory chip detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: May 12, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Drew G. Doblar, Gabriel C. Risk, Chung-Hsiao Wu
  • Patent number: 7527755
    Abstract: In one embodiment, a ferroelectric material is processed by placing the material in an environment including metal vapor and heating the material to a temperature below the Curie temperature of the material. This allows the bulk conductivity of the ferroelectric material to be increased without substantially degrading its ferroelectric domain properties. In one embodiment, the ferroelectric material comprises lithium tantalate and the metal vapor comprises zinc.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: May 5, 2009
    Assignee: Silicon Light Machines Corporation
    Inventors: Ronald O. Miles, Ludwig L. Galambos, Janos J. Lazar, Gabriel C. Risk, Alexei L. Alexandrovski, Gregory D. Miller, David Caudillo, Joseph M. McRae, Gisele L. Foulon
  • Publication number: 20090074049
    Abstract: A method, apparatus, and system for minimizing ringing in a high speed channel between a transmitter and a receiver in a circuit, including a component for initializing an n-tap equalization filter. The n-tap equalization filter includes numerous taps, each associated with each of numerous jitter pulses received from the transmitter at the receiver and over the channel. Many of the jitter pulses are greater than two. Further, each tap occurs at a time-domain point related to a time of a corresponding jitter pulse included within the numerous jitter pulses. Moreover, a component for applying the n-tap equalization filter to a subsequent signal sent over the channel is also included.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 19, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Gabriel C. Risk, Drew G. Doblar, Pruthvi A. Chaudhari
  • Patent number: 7437491
    Abstract: Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 14, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Gabriel C. Risk, Dawei Huang, Jason H. Bau
  • Patent number: 7409491
    Abstract: A memory system comprising memory modules including memory chips stacked with switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a stacked switching circuit detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple stacked switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: August 5, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Drew G. Doblar, Gabriel C. Risk, Chung-Hsiao R. Wu
  • Publication number: 20070280343
    Abstract: An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 6, 2007
    Inventors: Jason H. Bau, Drew G. Doblar, Gabriel C. Risk
  • Patent number: 7224638
    Abstract: A data communications system is disclosed. The data communications system comprises two clock domains. A first clock domain includes a transmitter and a first clock signal. A second clock domain includes a receiver and a second clock signal. The transmitter conveys the first clock signal and a data signal to the receiver. The receiver: (a) counts a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal; (b) maintains a first count of the number of transitions of the second clock signal; (c) samples the data signal and maintains a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value; and (d) samples the data signal and resets the second count in response to detecting the second count equals a second pre-determined value.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: May 29, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Gabriel C. Risk, Leandro A. Chua, Jr., Drew G. Doblar
  • Patent number: 6932957
    Abstract: In one embodiment, a ferroelectric material is processed by placing the material in an environment including metal vapor and heating the material to a temperature below the Curie temperature of the material. This allows the bulk conductivity of the ferroelectric material to be increased without substantially degrading its ferroelectric domain properties. In one embodiment, the ferroelectric material comprises lithium tantalate and the metal vapor comprises zinc.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: August 23, 2005
    Assignee: Silicon Light Machines Corporation
    Inventors: Ronald O. Miles, Ludwig L. Galambos, Janos J. Lazar, Gabriel C. Risk, Alexei L. Alexandrovski, Gregory D. Miller, David Caudillo, Joseph M. McRae, Gisele L. Foulon
  • Publication number: 20040163596
    Abstract: In one embodiment, a ferroelectric material is processed by placing the material in an environment including metal vapor and heating the material to a temperature below the Curie temperature of the material. This allows the bulk conductivity of the ferroelectric material to be increased without substantially degrading its ferroelectric domain properties. In one embodiment, the ferroelectric material comprises lithium tantalate and the metal vapor comprises zinc.
    Type: Application
    Filed: June 28, 2002
    Publication date: August 26, 2004
    Inventors: Ronald O. Miles, Ludwig L. Galambos, Janos J. Lazar, Gabriel C. Risk, Alexei L. Alexandrovski, Gregory D. Miller, David Caudillo, Joseph M. McRae, Gisele L. Foulon