Abstract: A computer-based software task management system includes an index register configured to store a data register pointer for pointing to a data register. A Task ID register is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a task ID memory.

Abstract: A computer-based software task management system (100) includes an index register (130) configured to store a data register pointer for pointing to a data register (150). A Task ID register (110) is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory (120) is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine (105) is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a Task ID memory. Advantages of the invention include the ability to efficiently manage a multithreaded operating system with virtually no additional software overhead.

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises dynamically adjusting the output voltage of the output drivers of one side of a bi-directional serial link down to the lowest voltage level that is able to maintain compliance with the error rate allowance threshold of the serial link, and operating the one side of the serial link at that voltage level.

Abstract: Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer register (52b) having a common register name. Processor (22) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register (52a) under a first condition and with stack pointer register (52b) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Abstract: Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer register (52b) having a common register name. Processor (22) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register (52a) under a first condition and with stack pointer register (52b) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Abstract: An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.

Abstract: A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis, maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on a time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache having various categories of instructions stores a group of status bits identifying the instruction category with each instruction.

Abstract: A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction.