Patents by Inventor Gang Ning

Gang Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11469019
    Abstract: An IM device includes a magnetic core including a base plate, a cover plate, and first, second and third magnetic columns. A straight line defined by positions of the first and second magnetic columns is parallel to a length direction, and the third magnetic column is between the first and second magnetic columns, and extends in a width direction. A first coil is wound around the first magnetic column to generate a closed magnetic flux loop, a second coil wound around the second magnetic column to generate a closed magnetic flux loop. The magnetic core includes a fourth magnetic column between the base plate and the cover plate, and close to a first terminal of the third magnetic column in the width direction. In the length direction, the fourth magnetic column overlaps with at least a portion of the first magnetic column and at least a portion of the second magnetic column.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: October 11, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Gang Li, Long Ning
  • Patent number: 11303712
    Abstract: An approach for service management in a distributed system may be provided. The approach may include obtaining a first service record for a first service that is deployed in a first cluster in a distributed system, the first service record may be represented in a global registry format defined in the distributed system. Additionally, the approach may include calling a first service entrance for the first service based on the first service record, the first service entrance may enable a second service, deployed in a second cluster in the distributed system, to call the first service. Further, the approach may include providing the first service entrance to the second cluster.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Guan Chao Li, Kun Yan Yin, Sheng Hui Zhan, Zhe Xue, Gang Ning
  • Publication number: 20210322417
    Abstract: Provided herein, in some embodiments, are methods, compositions, and kits for treating lapatinib-resistant gastric cancer.
    Type: Application
    Filed: April 30, 2021
    Publication date: October 21, 2021
    Applicant: The Jackson Laboratory
    Inventors: Chengsheng Zhang, Charles Lee, Gang Ning, Yun-Suhk Suh, Qihui Zhu
  • Patent number: 10811192
    Abstract: Multilayer ceramic capacitor structures may include structural arrangements, materials, and/or substrate modifications that can improve the reliability of the capacitor for long-term usage when faced with environmental stress. Embodiments may implement reduced entryways in the termination patterns of the capacitor to decrease damage potential due to exposure of moisture. Embodiments may implement structures that decrease interfaces with different physical characteristics, which may lead to a reduction in the formation of micro-fractures during regular usage. Methods of manufacture for the features that improve reliability are also detailed.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 20, 2020
    Assignee: Apple Inc.
    Inventors: Paul A. Martinez, Won Seop Choi, Gang Ning, Chirag V. Shah, Martin Schauer, Curtis C. Mead, Ming Yuan Tsai, Albert Wang
  • Patent number: 10712380
    Abstract: A method for fabricating a semiconductor structure includes when a chip under test releases an ESD current, detecting position information of photons emitted from the chip under test due to releasing of the ESD current; acquiring an image of an ESD path based on the detected position information of the photons; and determining whether the ESD path corresponding to the chip under test is normal based on the image of the ESD path and a layout image of the chip under test.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jun Wang, Gang Ning Wang, Mi Tang, Xian Yong Pu, Chengyu Zhu
  • Publication number: 20200105473
    Abstract: Multilayer ceramic capacitor structures may include structural arrangements, materials, and/or substrate modifications that can improve the reliability of the capacitor for long-term usage when faced with environmental stress. Embodiments may implement reduced entryways in the termination patterns of the capacitor to decrease damage potential due to exposure of moisture. Embodiments may implement structures that decrease interfaces with different physical characteristics, which may lead to a reduction in the formation of micro-fractures during regular usage. Methods of manufacture for the features that improve reliability are also detailed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Paul A. Martinez, Won Seop Choi, Gang Ning, Chirag V. Shah, Martin Schauer, Curtis C. Mead, Ming Yuan Tsai, Albert Wang
  • Publication number: 20200066457
    Abstract: Capacitors, including multilayer ceramic capacitors, may be subject to faults and failures that create short circuits between their dielectrics. Capacitors having fuses that protect the capacitors or the electrical devices using the capacitors when such faults occur are described herein. Embodiments include the presence of monolithic and non-monolithic structures including the fuse. Embodiments also include capacitors with multiple fuses that may prevent or mitigate capacitor failure. Methods for manufacturing and using the capacitors are also described.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Ching Yu John Tam, James John Ashe, Gang Ning, Won Seop Choi, Meng Chi Lee, Parin Patel, Samuel Benjamin Schaevitz, Derek J. DiCarlo
  • Publication number: 20180348279
    Abstract: A method for fabricating a semiconductor structure includes when a chip under test releases an ESD current, detecting position information of photons emitted from the chip under test due to releasing of the ESD current; acquiring an image of an ESD path based on the detected position information of the photons; and determining whether the ESD path corresponding to the chip under test is normal based on the image of the ESD path and a layout image of the chip under test.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 6, 2018
    Inventors: Jun WANG, Gang Ning WANG, Mi TANG, Xian Yong PU, Chengyu ZHU
  • Publication number: 20180144870
    Abstract: This application relates to multi-layered ceramic capacitors (MLCC) that can be surface mounted, include multiple terminals, and handle multiple voltages. The MLCC can include electrode and dielectric layers that are stacked in parallel to a printed circuit board (PCB) on which the MLCC can be attached. A set of primary conductive pads can be formed on the bottom of the MLCC in order to create a conductive interface between the PCB and the MLCC. Secondary conductive pads are formed on the side of the MLCC, and can extend perpendicular to the PCB. The secondary conductive pads are created by stacking internal electrode plates together and connecting them electrically and mechanically to each another. This arrangement provides for multiple voltages and electrical connections at the MLCC while reducing reverse piezoelectric and/or electro-striction noise.
    Type: Application
    Filed: January 17, 2018
    Publication date: May 24, 2018
    Applicant: Apple Inc.
    Inventors: Gang Ning, Shawn X. Arnold
  • Publication number: 20180061578
    Abstract: Passive component structures that may save space, are readily manufactured, and are easy to use. In one example, a passive component structure may include two capacitors, each formed as a group of plates separate and apart from the other. The two groups of plates may have a spacing layer between them.
    Type: Application
    Filed: September 1, 2017
    Publication date: March 1, 2018
    Applicant: Apple Inc.
    Inventors: Gang Ning, Paul A. Martinez, Amanda R. Rainer, Won Seop Choi, Gemin Li, Zhong-Qing Gong, Shawn X. Arnold
  • Patent number: 9859057
    Abstract: This application includes multiple embodiments related to capacitors. In some embodiments, capacitors are set forth as having terminal leads that extend in parallel and opposing axial directions. The embodiments discussed herein relate to a capacitor module including one or more anodized pellets for providing a charge storage within the capacitor module. The capacitor module can be configured as a surface mounted or non-surface mounted capacitor module. The capacitor module can include an array of anodized pellets arranged in multiple rows or columns of anodized pellets connected by conductive trace included in the capacitor module. In a non-surface mounted embodiment of the capacitor module, the capacitor module can include cathode and anode connections that are exclusively on the side surfaces of the capacitor module.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: January 2, 2018
    Assignee: Apple Inc.
    Inventors: Gang Ning, Raul A. Perez, Parin Patel
  • Patent number: 9715964
    Abstract: This disclosure describes methods and systems for minimizing electromagnetic interference (EMI) noise emanating from a ceramic capacitor. The ceramic capacitor may include several terminations are on a bottom portion of the capacitor. The capacitor may be designed to include several capacitors formed from electrode layers. The capacitor may include a conductive coating on an outer peripheral portion. The coating may include conductive materials such as Cu, Ni, Ag, and/or graphite. Alternatively, some regions of the capacitor may include electrode layers built into the capacitor that are not associated with capacitors. In this manner, the ceramic capacitor may be free of the conductive coating to locations proximate to the described electrode layers not associated with capacitors. The conductive coating can act as an electromagnetic shielding to prevent the EMI noise from emanating outside the electromagnetic shielding. Also, the conductive coating can be electrically grounded (e.g.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: July 25, 2017
    Assignee: Apple Inc.
    Inventors: Gang Ning, Pradeep Vengavasi, Linda Y. Dunn, Yonas A. Hartanto, Shawn X. Arnold
  • Publication number: 20170207024
    Abstract: Methods and devices related to fabrication and utilization of multilayer capacitors presenting low equivalent series resistance (ESR) is illustrated. The capacitors may present electrodes that are coupled to metallic terminations at the bottom and/or at the side of the capacitor. The position of the electrode coupling may lead to smaller current paths in the MLCC electrode, which may decrease line inductances. Methods and systems for fabrication of the capacitors described are also discussed.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 20, 2017
    Inventors: Paul A. Martinez, Gang Ning, Curtis C. Mead, Ming Y. Tsai, Albert Wang
  • Patent number: 9287049
    Abstract: The described embodiments relate generally to a capacitor assembly for mounting on a printed circuit board (PCB) and more specifically to designs for mechanically isolating the capacitor assembly from the PCB to reduce an acoustic noise produced when the capacitor imparts a piezoelectric force on the PCB. Termination elements in the capacitor assembly, including a porous conductive layer in the capacitor assembly may reduce an amount of vibrational energy transferred from the capacitor to the PCB. Termination elements including a soft contact layer may also reduce the amount of vibrational energy transferred to the PCB. Further, capacitor assemblies having thickened dielectric material may reduce the amount of vibrational energy transferred to the PCB.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: March 15, 2016
    Assignee: Apple Inc.
    Inventors: Gang Ning, Shawn Xavier Arnold, Jeffrey M. Thoma, Henry H. Yang
  • Publication number: 20160055975
    Abstract: This application includes multiple embodiments related to capacitors. In some embodiments, capacitors are set forth as having terminal leads that extend in parallel and opposing axial directions. The embodiments discussed herein relate to a capacitor module including one or more anodized pellets for providing a charge storage within the capacitor module. The capacitor module can be configured as a surface mounted or non-surface mounted capacitor module. The capacitor module can include an array of anodized pellets arranged in multiple rows or columns of anodized pellets connected by conductive trace included in the capacitor module. In a non-surface mounted embodiment of the capacitor module, the capacitor module can include cathode and anode connections that are exclusively on the side surfaces of the capacitor module.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 25, 2016
    Inventors: Cesar Lozano Villarreal, Gang Ning, Alexander Michael Kwan
  • Publication number: 20160055978
    Abstract: This application includes multiple embodiments related to capacitors. In some embodiments, capacitors are set forth as having terminal leads that extend in parallel and opposing axial directions. The embodiments discussed herein relate to a capacitor module including one or more anodized pellets for providing a charge storage within the capacitor module. The capacitor module can be configured as a surface mounted or non-surface mounted capacitor module. The capacitor module can include an array of anodized pellets arranged in multiple rows or columns of anodized pellets connected by conductive trace included in the capacitor module. In a non-surface mounted embodiment of the capacitor module, the capacitor module can include cathode and anode connections that are exclusively on the side surfaces of the capacitor module.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 25, 2016
    Inventors: Gang Ning, Raul A. Perez, Parin Patel
  • Publication number: 20150364255
    Abstract: This disclosure describes methods and systems for minimizing electromagnetic interference (EMI) noise emanating from a ceramic capacitor. The ceramic capacitor may include several terminations are on a bottom portion of the capacitor. The capacitor may be designed to include several capacitors formed from electrode layers. The capacitor may include a conductive coating on an outer peripheral portion. The coating may include conductive materials such as Cu, Ni, Ag, and/or graphite. Alternatively, some regions of the capacitor may include electrode layers built into the capacitor that are not associated with capacitors. In this manner, the ceramic capacitor may be free of the conductive coating to locations proximate to the described electrode layers not associated with capacitors. The conductive coating can act as an electromagnetic shielding to prevent the EMI noise from emanating outside the electromagnetic shielding. Also, the conductive coating can be electrically grounded (e.g.
    Type: Application
    Filed: September 29, 2014
    Publication date: December 17, 2015
    Inventors: Gang Ning, Pradeep Vengavasi, Linda Y. Dunn, Yonas A. Hartanto, Shawn X. Arnold
  • Publication number: 20150364253
    Abstract: Apparatus and methods are described for coupling a circuit component having piezoelectric properties, such as a ceramic capacitor, to a printed circuit board (PCB) by forming a first solder heel fillet and a second solder heel fillet that fixedly couple the circuit component to the PCB, where the first and second solder heel fillets have a height z that is less than a height h of the circuit component to reduce acoustic noise at the PCB caused by coupling the circuit component to the PCB. In various configurations, the first solder heel fillet and the second solder heel fillet can each fixedly coupled to: a bottom surface of the circuit component, a top surface of the PCB at a first solder pad and a second solder pad thereof, and a lower portion of each of a multiple side surfaces of the circuit component.
    Type: Application
    Filed: September 29, 2014
    Publication date: December 17, 2015
    Inventors: Shawn X. Arnold, Dennis R. Pyper, Gang Ning, Meng Chi Lee, Sascha Tietz, Sury N. Darbha, Zhong-Qing Gong
  • Publication number: 20150310991
    Abstract: This application relates to multi-layered ceramic capacitors (MLCC) that can be surface mounted, include multiple terminals, and handle multiple voltages. The MLCC can include electrode and dielectric layers that are stacked in parallel to a printed circuit board (PCB) on which the MLCC can be attached. A set of primary conductive pads can be formed on the bottom of the MLCC in order to create a conductive interface between the PCB and the MLCC. Secondary conductive pads are formed on the side of the MLCC, and can extend perpendicular to the PCB. The secondary conductive pads are created by stacking internal electrode plates together and connecting them electrically and mechanically to each another. This arrangement provides for multiple voltages and electrical connections at the MLCC while reducing reverse piezoelectric and/or electro-striction noise.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 29, 2015
    Applicant: Apple Inc.
    Inventors: Gang NING, Shawn X. ARNOLD
  • Publication number: 20140218841
    Abstract: The described embodiments relate generally to a capacitor assembly for mounting on a printed circuit board (PCB) and more specifically to designs for mechanically isolating the capacitor assembly from the PCB to reduce an acoustic noise produced when the capacitor imparts a piezoelectric force on the PCB. Termination elements in the capacitor assembly, including a porous conductive layer in the capacitor assembly may reduce an amount of vibrational energy transferred from the capacitor to the PCB. Termination elements including a soft contact layer may also reduce the amount of vibrational energy transferred to the PCB. Further, capacitor assemblies having thickened dielectric material may reduce the amount of vibrational energy transferred to the PCB.
    Type: Application
    Filed: April 26, 2013
    Publication date: August 7, 2014
    Applicant: Apple Inc.
    Inventors: Gang NING, Shawn Xavier ARNOLD, Jeffrey M. THOMA, Henry H. YANG