Patents by Inventor Gangyi Hu

Gangyi Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210305943
    Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor MO that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.
    Type: Application
    Filed: January 26, 2016
    Publication date: September 30, 2021
    Inventors: DAIGUO XU, GANGYI HU, RUZHANG LI, JIAN'AN WANG, GUANGBING CHEN, YUXIN WANG, TAO LIU, LU LIU, MINMING DENG, HANFU SHI, XU WANG
  • Patent number: 11121677
    Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: September 14, 2021
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Yuxin Wang, Tao Liu, Lu Liu, Minming Deng, Hanfu Shi, Xu Wang
  • Publication number: 20210281269
    Abstract: The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.
    Type: Application
    Filed: December 13, 2018
    Publication date: September 9, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Ting LI, Gangyi HU, Ruzhang LI, Yong ZHANG, Zhengbo HUANG, Yabo NI, Xingfa HUANG, Jian'an WANG, Guangbing CHEN, Dongbing FU, Jun YUAN, Zicheng XU
  • Publication number: 20210278867
    Abstract: The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.
    Type: Application
    Filed: December 13, 2018
    Publication date: September 9, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yan WANG, Gangyi HU, Tao LIU, Jian'an WANG, Daiguo XU, Guangbing CHEN, Dongbing FU
  • Publication number: 20210184689
    Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 17, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie PU, Gangyi HU, Dongbing FU, Zhengping ZHANG, Liang LI, Ting LI, Daiguo XU, Mingyuan XU, Xiaofeng SHEN, Xianjie WAN, Youhua WANG
  • Publication number: 20210135678
    Abstract: The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.
    Type: Application
    Filed: July 25, 2018
    Publication date: May 6, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie PU, Gangyi HU, Jian'an WANG, Guangbing CHEN, Liang LI, Ting LI, Daiguo XU, Xingfa HUANG, Xi CHEN, Tiehu LI, Youhua WANG
  • Patent number: 10944390
    Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 9, 2021
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Dongbing Fu, Shiliu Xu, Tao Liu, Jie Pu, Zhihua Feng
  • Publication number: 20200412353
    Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.
    Type: Application
    Filed: July 18, 2018
    Publication date: December 31, 2020
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIO
    Inventors: Daiguo XU, Gangyi HU, Ruzhang LI, Jian'an WANG, Guangbing CHEN, Dongbing FU, Shiliu XU, Tao LIU, Jie PU, Zhihua FENG
  • Patent number: 10778092
    Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 15, 2020
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Patent number: 10735018
    Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 4, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Publication number: 20200195270
    Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi
    Type: Application
    Filed: June 21, 2017
    Publication date: June 18, 2020
    Inventors: RONGBIN HU, YONGLU WANG, ZHENGPING ZHANG, JIAN'AN WANG, GUANGBING CHEN, DONGBING FU, YUXIN WANG, HEQUAN JIANG, GANGYI HU
  • Publication number: 20200127559
    Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
    Type: Application
    Filed: September 11, 2017
    Publication date: April 23, 2020
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Rongbin HU, Yonglu WANG, Zhengping ZHANG, Jian'an WANG, Guangbing CHEN, Dongbing FU, Yuxin WANG, Hequan JIANG, Gangyi HU
  • Publication number: 20200011911
    Abstract: A high-precision frequency measuring system and method. The system includes: an analog-to-digital conversion module for receiving an analog intermediate frequency signal to convert the analog intermediate frequency signal into a digital intermediate frequency signal; a frequency mixing module for generating two orthogonal local carriers to convert the digital intermediate frequency signal to a digital baseband signal; an extraction filter module for performing low-pass filtering and extraction of the digital baseband signal, so as to reduce a data rate; a Fourier transform module for obtaining a frequency domain signal; a frequency measurement module for obtaining a first frequency measurement value; a scanning module for obtaining a scanned second frequency measurement value; and a selector for selecting either the first frequency measurement value or the second frequency measurement value as a result of frequency measurement. The system and method can improve the accuracy of frequency measurement.
    Type: Application
    Filed: July 21, 2017
    Publication date: January 9, 2020
    Applicant: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yingtai LI, Gangyi HU, Luncai LIU, Fan LIU, Jian'an WANG, Xin LEI, Xiaozong HUANG, Guoqiang WANG, Jin ZHAO, Jianzhuang LI
  • Patent number: 10483358
    Abstract: A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 19, 2019
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou Tan, Gangyi Hu, Zhaohuan Tang, Jianan Wang, Yonghui Yang, Yi Zhong, Yang Cao, Yong Liu, Kunfeng Zhu
  • Patent number: 10425065
    Abstract: A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: September 24, 2019
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jianan Wang, Guangbing Chen, Yuxin Wang, Dongbing Fu, Tao Liu, Lu Liu, Minming Deng, Hanfu Shi, Xu Wang
  • Patent number: 10291245
    Abstract: The present invention provides a device and method for correcting error estimation of an analog-to-digital converter.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 14, 2019
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONIC TECHNOLOGY
    Inventors: Jie Pu, Gangyi Hu, Xiaofeng Shen, Xueliang Xu, Dongbing Fu, Ruitao Zhang, Youhua Wang, Yuxin Wang, Guangbing Chen, Ruzhang Li
  • Publication number: 20190115903
    Abstract: A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.
    Type: Application
    Filed: January 19, 2017
    Publication date: April 18, 2019
    Applicant: No. 24 Research Institute of China Electronics Technology Group Corporation
    Inventors: DAIGUO XU, GANGYI HU, RUZHANG LI, JIANAN WANG, GUANGBING CHEN, YUXIN WANG, DONGBING FU, TAO LIU, LU LIU, MINMING DENG, HANFU SHI, XU WANG
  • Publication number: 20190027563
    Abstract: A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 24, 2019
    Applicant: No. 24 Research Institute of China Electronics Technology Group Corporation
    Inventors: KAIZHOU TAN, GANGYI HU, ZHAOHUAN TANG, JIANAN WANG, YONGHUI YANG, YI ZHONG, YANG CAO, YONG LIU, KUNFENG ZHU
  • Patent number: 10181821
    Abstract: The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors M1 and M2, a first-stage active load consisting of PMOS transistors M3 and M4, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M5, a second-stage constant current source consisting of an NMOS transistor M6, a load capacitor consisting of a capacitor CL, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 15, 2019
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION 24TH RESEARCH INSTITUTE
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Yuxin Wang, Tao Liu, Lu Liu, Minming Deng, Hanfu Shi, Xu Wang
  • Publication number: 20180358976
    Abstract: A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimat
    Type: Application
    Filed: August 20, 2015
    Publication date: December 13, 2018
    Applicant: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie PU, Gangyi HU, Xiaofeng SHEN, Xueliang XU, Dongbing FU, Ruitao ZHANG, Youhua WANG, Yuxin WANG, Guangbing CHEN, Ruzhang LI