Patents by Inventor Garvin Wesley Patterson

Garvin Wesley Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4099234
    Abstract: An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit.
    Type: Grant
    Filed: November 15, 1976
    Date of Patent: July 4, 1978
    Assignee: Honeywell Information Systems Inc.
    Inventors: John M. Woods, Marion G. Porter, Donald V. Mills, Edward F. Weller, III, Garvin Wesley Patterson, Earnest M. Monahan
  • Patent number: 4010450
    Abstract: A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.
    Type: Grant
    Filed: March 26, 1975
    Date of Patent: March 1, 1977
    Assignee: Honeywell Information Systems, Inc.
    Inventors: Marion G. Porter, Garvin Wesley Patterson, Jaime Calle
  • Patent number: 4006466
    Abstract: An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations.
    Type: Grant
    Filed: March 26, 1975
    Date of Patent: February 1, 1977
    Assignee: Honeywell Information Systems, Inc.
    Inventors: Garvin Wesley Patterson, William A. Shelly, Jaime Calle, Earnest M. Monahan
  • Patent number: 4001788
    Abstract: A microprogram control system includes first and second control stores. The first is a pathfinder control store which is addressed initially by the operation code of a program instruction for read out of first and second addresses. The first address is used for accessing a standard microinstruction sequence during a first phase of operation. The second address is used for accessing an execution microinstruction sequence during a second phase of operation, both phases being required for executing the operation specified by the operation code of the program instruction. Means coupled to the second control store enable the control store to return to the standard microinstruction sequence following the completion of the second phase of operation when the instruction being executed requires the completion of additional operations before its execution can be terminated.
    Type: Grant
    Filed: March 26, 1975
    Date of Patent: January 4, 1977
    Assignee: Honeywell Information Systems, Inc.
    Inventors: Garvin Wesley Patterson, Marion G. Porter
  • Patent number: 4000487
    Abstract: An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated.
    Type: Grant
    Filed: March 26, 1975
    Date of Patent: December 28, 1976
    Assignee: Honeywell Information Systems, Inc.
    Inventors: Garvin Wesley Patterson, William A. Shelly, Earnest M. Monahan
  • Patent number: 3976977
    Abstract: An input-output processing system (IOPS) which performs both the communication and control functions in a large scale data processing system is disclosed. By relieving the main data processor of these functions more efficient use of the entire system is made possible. The IOPS includes a processor to develop addresses for a paged memory and institute execution of input-output command sequences.
    Type: Grant
    Filed: March 26, 1975
    Date of Patent: August 24, 1976
    Assignee: Honeywell Information Systems, Inc.
    Inventors: Marion G. Porter, Garvin Wesley Patterson, William A. Shelly, Nicolas S. Lemak
  • Patent number: 3976978
    Abstract: An input-output processing system which performs communication and control functions in a larger data processing system includes a processor for address development to paged memory and program instruction execution for I/O command sequences. In generating memory addresses, instructions are provided an address syllable which references a processor register as an index and a displacement. The contents of the register and the displacement define a memory effective address. A scratchpad memory is provided for storing page table words in levels corresponding to priority levels of processes, and stored page table words are accessed according to the least significant bits of the page number of the effective address. A page base address is taken from an accessed page table word and is concatenated with the effective address to define an absolute memory address.
    Type: Grant
    Filed: March 26, 1975
    Date of Patent: August 24, 1976
    Assignee: Honeywell Information Systems, Inc.
    Inventors: Garvin Wesley Patterson, Marion G. Porter