Abstract: This invention provides a flash memory cell structure comprising a semiconductor substrate; a tunneling oxide layer formed above the substrate and having a long narrow top profile; a gate oxide layer formed above the substrate on each side of the tunneling oxide layer; a bottom conductive layer formed above the substrate and surrounded the gate oxide layer; and a stacked gate formed above the tunneling oxide layer, the gate oxide layer and the bottom conductive layer, wherein there is an insulating layer between the stacked gate and the bottom conductive layer for electrically isolating the stacked gate from the bottom conductive layer, and that the stacked gate further comprises a floating gate, a dielectric layer and a control gate.

Abstract: A method for forming a well structure in an integrated circuit such that, without any additional masking steps, the well implantation can be performed before the definition of the active device area. Hence, besides being able to avoid problems caused by a low breakdown voltage, also can provide a self-alignment mark for subsequent mask alignment, thereby reducing misalignment errors.

Abstract: A MOSFET device on a lightly doped semiconductor substrate comprises forming a dielectric layer on the substrate, a floating gate layer over the dielectric layer, a sacrificial layer on the floating gate layer, and a split-gate channel mask patterned with openings over the sacrificial layer.

Abstract: A high capacitance DRAM structure is provided for a capacitor over bit line DRAM structure. A planarized dielectric layer is provided over the transfer FETs and the bit line contact of a COB structure. A silicon nitride layer is provided over the planarized dielectric layer to serve as an etch stop for a subsequent wet etching process. A first sacrificial oxide layer is deposited over the silicon nitride etch stop layer and then contacts are opened through the various dielectric layers to the appropriate source/drain regions of the transfer FETs. A first polysilicon layer is deposited within the capacitor contact openings and over the first sacrificial oxide layer. A second sacrificial oxide layer is provided and openings are formed in the second sacrificial oxide layer substantially centered over the capacitor contacts. A second polysilicon layer is provided over the second sacrificial oxide layer and in contact with the first polysilicon layer.

Abstract: A method for fabricating flash memory cells having a DDD structure that prevents leakage current during data erasure, that does not require a high temperature drive-in process, and that easily combines with other logic processes. The method for fabricating the flash memory cells utilizes ion implantation through contact windows to establish heavily doped source and drain regions inside previously formed deeply doped source and drain regions to construct the DDD structure.

Abstract: A narrow gate FET is formed on a substrate by providing a first layer of polysilicon on the active device regions of the substrate and doping the polysilicon by ion implantation. An etch/polish stop layer of silicon oxide and is deposited on the first layer of polysilicon. Openings are formed in the etch/polish stop layer and the first polysilicon layer to expose the surface of the substrate. An anneal is performed to diffuse N-type impurities from the first layer of polysilicon into the substrate. The heavily doped portions of LDD source/drain regions are formed partially within the substrate and partially within portions of the first layer of polysilicon left on the surface of the substrate. Next, a first implantation of N-type impurities is made across the opening in the first layer of polysilicon. A layer of silicon nitride is deposited over the first layer of polysilicon and within the openings in the first polysilicon layer.

Abstract: A process for fabricating compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units is disclosed. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed.

Abstract: A method of fabricating a buried bit line. An insulating layer is formed on a substrate, a trench is formed within the substrate by patterning the insulating layer and the substrate and then a liner oxide is formed on the trench surface. Then, a first conductive layer is formed on the insulating layer to cover the liner oxide layer and fills the trench. A portion of the first conductive layer is removed, exposing a portion of the liner oxide layer. Next, the exposed liner oxide layer is removed to form a space which, along with the trench, is filled with a second conductive layer on the insulating layer. Ion implantation and annealing is performed to form a shallow junction region in the substrate and the shallow junction region makes contact with the second conductive layer.

Abstract: A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

Abstract: A method of fabricating a flash memory having a vertical floating gate terminal layer and controlling gate terminal layer structure, which is suitable for use in ultra-high density IC circuits, and which has two separate tunneling layers, one used for data programming and the other used for data erasure. The fabrication method includes a number of steps. A protruding plateau is first formed on the surface of a silicon substrate. Then, ions are implanted to form a drain region on the top surface of the protruding plateau, as well as to form source regions in the substrate on each side of and adjacent to the base of the protruding plateau. A gate oxide layer is formed on each side wall of the protruding plateau; exposing only part of the side wall of the drain region. A tunnel oxide layer that is thinner than the gate oxide layer, is formed above the surface of the silicon substrate so as to cover the source regions and drain region.

Abstract: A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.

Abstract: A method for fabricating compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.

Abstract: A method of fabricating a DRAM which includes a capacitor and a metal oxide semiconductor field effect transistor. A field oxide layer is formed on a silicon substrate. A gate oxide layer is formed on the silicon substrate. A first polysilicon layer is deposited on the gate oxide layer. An insulator is deposited on the first polysilicon layer. A first silicon nitride layer is deposited on the insulator. The first silicon nitride layer, the insulator, the first polysilicon layer and the gate oxide layer are processed to form a gate electrode. First spacers are formed between the insulator and the substrate on sidewall on opposite sides of the gate electrode. Source-drain regions are formed on the substrate on the opposite sides of the gate electrode. A contact window is formed on the drain electrode. Second spacers are formed on surfaces of the first spacers which are adjacent to the contact window.

Abstract: A process for fabricating an improved planar field oxide (FOX) structure on a silicon substrate was achieved. The process involves forming recessed areas in the silicon substrate where the field oxide is require. A thin silicon oxide is formed on the surface of the recessed areas as a nucleation layer and then a thicker silicon oxide layer is selectively deposited in the recess areas by Liquid Phase Deposition (LPD). The planar FOX structure formed by LPD can be used in conjunction with a FOX structure formed by the conventional LOCal Oxidation of Silicon (LOCOS) process on the same substrate. The planar field oxide formed by LPD eliminates the bird beak structure and the lateral diffusion of the channel stop implant commonly associated with the LOCOS structure.

Abstract: A FET is formed that occupies a reduced surface area on a substrate because it incorporates elevated source/drain contacts provided at least partially over the field oxide regions. A silicon nitride mask is formed over the substrate and the mask is used for defining field oxide regions. Trenches are etched on either side of the mask and then thermal oxidation grows field oxide regions in the trenches so that the surface of the field oxide regions are approximately even with the original surface of the substrate. With the silicon nitride mask still in place, polysilicon is deposited over the substrate. The device is then planarized to remove the polysilicon from surfaces of the substrate, exposing the surface of the mask and leaving polysilicon structures on the field oxide regions on either side of mask. The mask is stripped and a layer of silicon is deposited over the polysilicon structures and on the active device region of the substrate, where the deposited silicon is epitaxial.

Abstract: A compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed.

Abstract: A compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.

Abstract: A process of fabricating a flash EEPROM having a NAND structure by using the liquid phase deposition (LPD) technique and self-alignment technique is disclosed to achieve higher density and reliability of flash memory cells and eliminating the shortcomings of the bird's beaks of field oxides.

Abstract: In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

Abstract: A process for forming an EEPROM having silicon rich tunnel oxide is disclosed. This oxide is used in the formation of flash EEPROMs and results in high tunneling current at low voltages. The oxide also results in EEPROMs having good endurance. A layer of silicon enriched with oxygen is formed between the substrate and the insulating layer separating the substrate from the floating gate.