Patents by Inventor Gary J. Sgrignoli

Gary J. Sgrignoli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7313208
    Abstract: A low cost DTV translator, which translates an incoming signal on channel A to an outgoing signal on channel B, includes a transmitter pre-equalizer whose taps are configured with tap values that pre-distort a signal so as to negate distortion caused by a high power amplifier and emission mask filter at the output of the DTV translator. This pre-distortion is accomplished by using the transmitter of the DTV translator to provided a reference signal and to use the receiver of the DTV translator as a reference receiver for the reference signal to thereby avoid the use of a more expensive external reference receiver.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: December 25, 2007
    Assignee: Zenith Electronics Corporation
    Inventors: Timothy V. Frahm, Gary J. Sgrignoli
  • Patent number: 6295015
    Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: September 25, 2001
    Assignee: Zenith Electronics Corporation
    Inventors: Gary A. Jones, Gary J. Sgrignoli, Minglu Zhang
  • Patent number: 6166594
    Abstract: A reference signal source produces a substantially distortion free reference signal which is supplied to a demodulator that is arranged to demodulate the substantially distortion free reference signal. A calibration filter and an equalizer are included downstream of the demodulator. A controller sets the calibration filter to initially pass the reference signal to the equalizer without substantial change to the reference signal. The controller subsequently calibrates the calibration filter in accordance with the demodulator caused distortion reduced by the equalizer.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: December 26, 2000
    Assignee: Zenith Electronics Corporation
    Inventors: Larry E. Nielsen, Gary J. Sgrignoli
  • Patent number: 6069524
    Abstract: A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: May 30, 2000
    Assignee: Zenith Electronics Corporation
    Inventors: Victor G. Mycynek, Gary J. Sgrignoli
  • Patent number: 5821988
    Abstract: A digital television receiver operating in the presence of an NTSC co-channel signal includes an NTSC rejection filter that is selectively inserted in the digital television signal path to minimize interference from the NTSC co-channel signal. The energy around the NTSC picture carrier is sampled. This is compared with sampled white noise energy between the NTSC picture and color carriers, after field combing the digital television signal to eliminate the effects of static signals. The comparison is used to determine whether or not the NTSC rejection filter is inserted in the digital television signal path.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: October 13, 1998
    Assignee: Zenith Electronics Corporation
    Inventors: Richard W. Citta, Larry E. Nielsen, Gary J. Sgrignoli
  • Patent number: 5699011
    Abstract: A DC offset measurement and compensation circuit includes a switch arrangement for establishing a zero carrier condition in the circuit. The circuit output is integrated to develop any DC offsets, which are converted to analog form and subtracted from the signal output. A reference may also be subtracted to establish a base digital level for the output.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: December 16, 1997
    Assignee: Zenith Electronics Corporation
    Inventor: Gary J. Sgrignoli
  • Patent number: 5675283
    Abstract: A polarity detection circuit for an FPLL demodulated signal including a small DC pilot recovers the DC pilot by determining the DC levels of the demodulated output signals both with and without the DC pilot. A zero carrier condition is created for determining the DC level of the output signal without the DC pilot. The two DC levels are subtracted and limited and the polarity of the recovered DC pilot is used to control the operation of a polarity inverter to assure that the output signal has a desired polarity.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: October 7, 1997
    Assignee: Zenith Electronics Corporation
    Inventor: Gary J. Sgrignoli
  • Patent number: 5675284
    Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock indicator circuit determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming signal (or alternatively, of the outgoing signal) as determined in order to supply an output signal of predetermined polarity. The frequency lock indicator consists of a zero crossings detector and a latch that is sampled for a time period. The zero crossings detector is a delay and an exclusive OR gate. An optional confidence counter may be used with the latch to determine when frequency lock has occurred to provide the lock indicator signal.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: October 7, 1997
    Assignee: Zenith Electronics Corporation
    Inventor: Gary J. Sgrignoli
  • Patent number: 5668498
    Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock circuit also determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming, or alternatively, of the outgoing signal, as determined in order to supply an output signal of predetermined polarity.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: September 16, 1997
    Assignee: Zenith Electronics Corporation
    Inventor: Gary J. Sgrignoli
  • Patent number: 5642154
    Abstract: A cable system includes a cable head end and a plurality of distribution sites having equipment for supplying subscriber station receivers with digital video cable signals from the cable head end. The digital video signal includes a robust data component that is receivable by distribution site receivers and cable subscriber station receivers under very poor carrier-to-noise conditions, that is, where the video signal itself is not usable. The cable head end has capabilities for interrogating distribution site receivers and subscriber station receivers which respond by transmitting designated information concerning differences between the received robust data component and the transmitted robust data component. At the subscriber station receivers, the robust data component is in the form of a training sequence of known characteristics that is compared with a received training sequence.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: June 24, 1997
    Assignee: Zenith Electronics Corporation
    Inventors: Gopalan Krishnamurthy, Gary J. Sgrignoli
  • Patent number: 5638140
    Abstract: An AFC filter for an FPLL comprises a filter formed of a network of resistors and capacitors exhibiting a predetermined phase response characteristic. The phase response characteristic is limited with increasing frequency to a value of about 90.degree. during a start-up interval.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: June 10, 1997
    Assignee: Zenith Electronics Corporation
    Inventors: Gopalan Krishnamurthy, Victor G. Mycynek, Gary J. Sgrignoli
  • Patent number: 5627604
    Abstract: A bi-phase stable FPLL is locked by a DC pilot component in a recovered data signal. The signal is formatted in repetitive data segments including sync characters and a DC pilot. A sign bit, indicative of the polarity of the recovered data, is developed from the sync characters and is used to augment the DC pilot to stabilize the lock up of the FPLL to produce the desired polarity of recovered data.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: May 6, 1997
    Assignee: Zenith Electronics Corporation
    Inventors: Gopalan Krishnamurthy, Victor G. Mycynek, Gary J. Sgrignoli
  • Patent number: 5598220
    Abstract: A digital video field identification system includes video signals formatted in blocks of video symbols in repetitive data segments with each data segment including a synchronizing signal character. One data segment includes a field timing signal. A reference data segment which includes a reference field timing signal is developed at the receiver. A portion of each data segment is compared with the reference field timing signal and the number of symbol errors is accumulated for each data segment. The data segment exhibiting the least number of symbol errors is identified as the one having the field timing signal. A confidence counter stabilizes the identification of the one data segment. For terrestrial transmission, the video signals are precoded in modulo N form to enable NTSC co-channel interference rejection in the receiver by a linear filter.
    Type: Grant
    Filed: March 2, 1994
    Date of Patent: January 28, 1997
    Assignee: Zenith Electronics Corporation
    Inventors: Richard W. Citta, Gary J. Sgrignoli, Rudolf Turner
  • Patent number: 5594496
    Abstract: A receiver receives an ATV (e.g. HDTV) signal in an area that is subject to NTSC co-channel and other interference. The received signal is precoded at the transmitter for enabling reduction of NTSC co-channel interference in the received signal. The received signal includes field sync signals that are successively field combed to produce a subtraction signal. The subtraction signal is comb filtered to reduce NTSC co-channel interference and applied to a comparator along with the unfiltered subtraction signal. The comparator determines whether the level of NTSC co-channel interference is sufficiently great to subject the received ATV signal to comb filtering for reducing the NTSC co-channel interference.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 14, 1997
    Assignee: Zenith Electronics Corporation
    Inventors: Larry E. Nielsen, Gary J. Sgrignoli
  • Patent number: 5574509
    Abstract: An antenna adjustment system for a digital television receiver includes a graphics generator for receiving an error signal input and developing an on-screen signal quality display. An antenna is positionable by the viewer while referring to the on-screen signal quality display which enables optimal orientation of the antenna for best signal quality. The error signal is developed by comparing a rugged frame sync in the received television signal with a reference frame sync in the television receiver.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: November 12, 1996
    Assignee: Zenith Electronics Corporation
    Inventors: Richard W. Citta, Gary J. Sgrignoli
  • Patent number: 5565932
    Abstract: An AGC circuit for a digital receiver that receives a digital television signal or the like, including a pilot, and formatted in a plurality of repetitive data segments, each data segment comprising a fixed number of multilevel symbols occurring at a constant symbol rate. The multilevel symbols are converted to corresponding digital values and the pilot (represented by a DC offset) is removed from the digital values. Every fourth symbol is sampled and the samples are accumulated and divided to derive an average symbol value. The average symbol value is compared with a reference average symbol value and the result of the comparison is an AGC potential that controls the tuner and IF gains. A cable/terrestrial input alters the sampling for cable signals to compensate for high level sweep testing in cable systems.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: October 15, 1996
    Assignee: Zenith Electronics Corp.
    Inventors: Richard W. Citta, Dennis M. Mutzabaugh, Gary J. Sgrignoli
  • Patent number: 5546138
    Abstract: A dual mode AGC system for a television receiver in which data is in the form of symbols occurring at a fixed symbol rate. The symbols are sent in successive data segments, each having a sync character. Enablement of an AFC Defeat signal defines an initial interval during which the IF gain is maximum. When the AFC Defeat signal becomes inactive, the receiver is operated in a non-coherent mode in which the gain of the IF amplifier is reduced incrementally whenever the IF signal exceeds a clipping level for a period of eight successive symbol clocks. Upon a segment sync lock condition occurring, a normal coherent mode is entered in which the AGC responds to a signal characteristic, i.e. data segment sync. The rate of gain change available in the non-coherent mode-is much greater than that in the normal coherent mode.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: August 13, 1996
    Assignee: Zenith Electronics Corporation
    Inventors: Gopalan Krishnamurthy, Victor G. Mycynek, Gary J. Sgrignoli
  • Patent number: 5534938
    Abstract: A digital data transmission system includes data signals formatted in successive fields consisting of blocks of video symbols in repetitive data segments with each data segment including a synchronizing signal character for providing data segment sync. The first data segment in each field includes a field timing signal that provides field sync. The digital data is in the form of M-level symbols and the sync information (both data segment and field) is in the form of N-level symbols, where M is greater than N.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: July 9, 1996
    Inventors: Richard W. Citta, Gary J. Sgrignoli, Rudolf Turner
  • Patent number: 5416524
    Abstract: A digital television signal includes data sent as multilevel symbols in successive data segments each including a synchronizing sync character. The detected synchronizing sync character produces a characteristic having two opposite polarity levels separated by a zero reference level, with the levels occurring at successive sampling points of the television signal, and a detection signal that has a peak occurring in time coincidence with the zero reference level. The detection signal controls sampling of the received television signal. The gain of the received signal is controlled by an AGC circuit that also responds to the detection signal.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: May 16, 1995
    Assignee: Zenith Electronics Corp.
    Inventors: Richard W. Citta, Dennis M. Mutzabaugh, Gary J. Sgrignoli
  • Patent number: RE36992
    Abstract: A television signal transmission signal comprises a suppressed carrier, VSB signal having respective Nyquist slopes at the lower and upper edges of a 6 MHz television channel, the center frequency of the Nyquist slope at the lower edge of the channel being substantially coincident with the frequency of the suppressed carrier, and a pilot signal in quadrature relation with the suppressed carrier. The suppressed carrier is modulated by an N-level digitally encoded signal having a sample rate fs substantially equal to three times the NTSC color subcarrier frequency, with the frequency of the color subcarrier being less than the co-channel NTSC picture carrier by an amount equal to about fs/12. The received signal is demodulated by a synchronous detector in response to the received pilot signal and interfering NTSC beat components are attenuated by a linear filter having notches at fs/12, 5fs/12 and fs/2.
    Type: Grant
    Filed: February 9, 1994
    Date of Patent: December 19, 2000
    Assignee: Zenith Electronics Corporation
    Inventors: Richard W. Citta, Dennis M. Mutzabaugh, Gary J. Sgrignoli