Patents by Inventor Gary Matsunami

Gary Matsunami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10733351
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. In particular, the present embodiments allow for the automatic creation of WSPs by examining heights and placement orientations of instances, along with the width, spacing, and colors of instance pins and blockages. In these and other embodiments, techniques are provided for filling gaps between generated tracks, as well as for generating tracks to account for the possibility of flipped or mirrored instances.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: August 4, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gary Matsunami, Karun Sharma, Sandipan Ghosh, Yinnie Lee
  • Patent number: 10452806
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various alternatives for identifying starting points in the design for automatically generating track patterns are possible.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 22, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sabra Rossman, Gary Matsunami, Karun Sharma, Steven Riley, Joshua A. Baudhuin
  • Patent number: 9754072
    Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 5, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami
  • Patent number: 9384317
    Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 5, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami