Abstract: The present invention reduces certain unwanted transients in an output stage by sensing the power supply and disabling the output stage output devices in correlation with the sensing of an invalid bias. In preferred embodiments, the bias is measured at a node that is the last bias node to reach a steady state during power up or power glitches. This ensures that all portions of the output stage are being provided a valid bias prior to enabling the output devices of the output stage. By enabling the output devices only after a valid bias is present, signals generated by the output devices are based upon valid operation of the output stage.

Abstract: A reset circuit for a phase detector in a phase-locked loop is described. A first set of input lines receives a first set of latched signals corresponding to a cycle of a reference signal applied to the phase detector of the phase-locked loop. Reset assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to generate a reset signal that is applied to an output node. The generated reset signal has a cycle duration corresponding to the reference signal cycle duration. Reset de-assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to de-assert the generated reset signal after a period of time corresponding to the reference signal cycle duration. Similar processing may be performed in relation to a second set of latched signals corresponding to a cycle of a feedback signal applied to the phase detector of the phase-locked loop.