Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Various embodiments are generally directed to generating logs recording events related to wakelocks at application and kernel levels, and then temporally aligning graphs of those events in a visual presentation to enable debugging of wakelocks. An apparatus to debug wakelocks includes a processor component; a capture component to intercept calls associated with application level wakelocks, the intercepted calls received by an application power manager of an operating system from application routines; and a relaying component to cooperate with the application power manager to provide indications of the intercepted calls to a system log generator of the operating system coupled to the application power manager, the system log generator to generate system log data comprising indications of events associated with execution of the operating system by the processor component and the indications of the intercepted calls. Other embodiments are described and claimed.

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Various embodiments are generally directed to generating logs recording events related to wakelocks at application and kernel levels, and then temporally aligning graphs of those events in a visual presentation to enable debugging of wakelocks. An apparatus to debug wakelocks includes a processor component; a capture component to intercept calls associated with application level wakelocks, the intercepted calls received by an application power manager of an operating system from application routines; and a relaying component to cooperate with the application power manager to provide indications of the intercepted calls to a system log generator of the operating system coupled to the application power manager, the system log generator to generate system log data comprising indications of events associated with execution of the operating system by the processor component and the indications of the intercepted calls. Other embodiments are described and claimed.

Abstract: A method for detecting race conditions in a concurrent processing environment is provided. The method comprises implementing a data structure configured for storing data related to at least one task executed in a concurrent processing computing environment, each task represented by a node in the data structure; and assigning to a node in the data structure at least one of a task number, a wait number, and a wait list; wherein the task number uniquely identifies the respective task, wherein the wait number is calculated based on a segment number of the respective task's parent node, and wherein the wait list comprises at least an ancestor's wait number. The method may further comprise monitoring a plurality of memory locations to determine if a first task accesses a first memory location, wherein said first memory location was previously accessed by a second task.

Abstract: A method for detecting race conditions in a concurrent processing environment is provided. The method comprises implementing a data structure configured for storing data related to at least one task executed in a concurrent processing computing environment, each task represented by a node in the data structure; and assigning to a node in the data structure at least one of a task number, a wait number, and a wait list; wherein the task number uniquely identifies the respective task, wherein the wait number is calculated based on a segment number of the respective task's parent node, and wherein the wait list comprises at least an ancestor's wait number. The method may further comprise monitoring a plurality of memory locations to determine if a first task accesses a first memory location, wherein said first memory location was previously accessed by a second task.